// ======================================================================
// SimpleSDR_PSoC.v generated from TopDesign.cysch
// 03/16/2012 at 15:21
// ======================================================================

/* -- WARNING: The following section of defines are deprecated and will be removed in a future release -- */
`define CYDEV_CHIP_DIE_LEOPARD 1
`define CYDEV_CHIP_REV_LEOPARD_PRODUCTION 3
`define CYDEV_CHIP_REV_LEOPARD_ES3 3
`define CYDEV_CHIP_REV_LEOPARD_ES2 1
`define CYDEV_CHIP_REV_LEOPARD_ES1 0
`define CYDEV_CHIP_DIE_PANTHER 2
`define CYDEV_CHIP_REV_PANTHER_PRODUCTION 1
`define CYDEV_CHIP_REV_PANTHER_ES1 1
`define CYDEV_CHIP_REV_PANTHER_ES0 0
`define CYDEV_CHIP_DIE_EXPECT 1
`define CYDEV_CHIP_REV_EXPECT 3
`define CYDEV_CHIP_DIE_ACTUAL 1
/* -- WARNING: The previous section of defines are deprecated and will be removed in a future release -- */
`define CYDEV_CHIP_FAMILY_UNKNOWN 0
`define CYDEV_CHIP_MEMBER_UNKNOWN 0
`define CYDEV_CHIP_FAMILY_PSOC3 1
`define CYDEV_CHIP_MEMBER_3A 1
`define CYDEV_CHIP_REVISION_3A_PRODUCTION 3
`define CYDEV_CHIP_REVISION_3A_ES3 3
`define CYDEV_CHIP_REVISION_3A_ES2 1
`define CYDEV_CHIP_REVISION_3A_ES1 0
`define CYDEV_CHIP_FAMILY_PSOC5 2
`define CYDEV_CHIP_MEMBER_5A 2
`define CYDEV_CHIP_REVISION_5A_PRODUCTION 1
`define CYDEV_CHIP_REVISION_5A_ES1 1
`define CYDEV_CHIP_REVISION_5A_ES0 0
`define CYDEV_CHIP_FAMILY_USED 1
`define CYDEV_CHIP_MEMBER_USED 1
`define CYDEV_CHIP_REVISION_USED 3
// Component: cy_analog_virtualmux_v1_0
`ifdef CY_BLK_DIR
`undef CY_BLK_DIR
`endif

`ifdef WARP
`define CY_BLK_DIR "$CYPRESS_DIR\..\psoc\content\cyprimitives\CyPrimitives.cylib\cy_analog_virtualmux_v1_0"
`include "$CYPRESS_DIR\..\psoc\content\cyprimitives\CyPrimitives.cylib\cy_analog_virtualmux_v1_0\cy_analog_virtualmux_v1_0.v"
`else
`define CY_BLK_DIR "C:\Program Files (x86)\Cypress\PSoC Creator\2.0\PSoC Creator\psoc\content\cyprimitives\CyPrimitives.cylib\cy_analog_virtualmux_v1_0"
`include "C:\Program Files (x86)\Cypress\PSoC Creator\2.0\PSoC Creator\psoc\content\cyprimitives\CyPrimitives.cylib\cy_analog_virtualmux_v1_0\cy_analog_virtualmux_v1_0.v"
`endif

// Component: cy_virtualmux_v1_0
`ifdef CY_BLK_DIR
`undef CY_BLK_DIR
`endif

`ifdef WARP
`define CY_BLK_DIR "$CYPRESS_DIR\..\psoc\content\cyprimitives\CyPrimitives.cylib\cy_virtualmux_v1_0"
`include "$CYPRESS_DIR\..\psoc\content\cyprimitives\CyPrimitives.cylib\cy_virtualmux_v1_0\cy_virtualmux_v1_0.v"
`else
`define CY_BLK_DIR "C:\Program Files (x86)\Cypress\PSoC Creator\2.0\PSoC Creator\psoc\content\cyprimitives\CyPrimitives.cylib\cy_virtualmux_v1_0"
`include "C:\Program Files (x86)\Cypress\PSoC Creator\2.0\PSoC Creator\psoc\content\cyprimitives\CyPrimitives.cylib\cy_virtualmux_v1_0\cy_virtualmux_v1_0.v"
`endif

// Component: ZeroTerminal
`ifdef CY_BLK_DIR
`undef CY_BLK_DIR
`endif

`ifdef WARP
`define CY_BLK_DIR "$CYPRESS_DIR\..\psoc\content\cyprimitives\CyPrimitives.cylib\ZeroTerminal"
`include "$CYPRESS_DIR\..\psoc\content\cyprimitives\CyPrimitives.cylib\ZeroTerminal\ZeroTerminal.v"
`else
`define CY_BLK_DIR "C:\Program Files (x86)\Cypress\PSoC Creator\2.0\PSoC Creator\psoc\content\cyprimitives\CyPrimitives.cylib\ZeroTerminal"
`include "C:\Program Files (x86)\Cypress\PSoC Creator\2.0\PSoC Creator\psoc\content\cyprimitives\CyPrimitives.cylib\ZeroTerminal\ZeroTerminal.v"
`endif

// ADC_DelSig_v2_20(ADC_Charge_Pump_Clock=false, ADC_Clock=1, ADC_CLOCK_FREQUENCY=6000082, ADC_Input_Mode=0, ADC_Input_Range=4, ADC_Input_Range_Config2=4, ADC_Input_Range_Config3=4, ADC_Input_Range_Config4=4, ADC_Power=1, ADC_Reference=1, ADC_Reference_Config2=1, ADC_Reference_Config3=0, ADC_Reference_Config4=0, ADC_Resolution=14, ADC_Resolution_Config2=14, ADC_Resolution_Config3=16, ADC_Resolution_Config4=16, Clock_Frequency=64000, Comment_Config1=Default Config, Comment_Config2=Second Config, Comment_Config3=Third Config, Comment_Config4=Fourth Config, Config1_Name=CFG1, Config2_Name=CFG2, Config3_Name=CFG3, Config4_Name=CFG4, Configs=1, Conversion_Mode=1, Conversion_Mode_Config2=1, Conversion_Mode_Config3=2, Conversion_Mode_Config4=2, Debug=false, DsmName=DSM4, Enable_Vref_Vss=false, Input_Buffer_Gain=1, Input_Buffer_Gain_Config2=1, Input_Buffer_Gain_Config3=1, Input_Buffer_Gain_Config4=1, Input_Buffer_Mode=0, Input_Buffer_Mode_Config2=0, Input_Buffer_Mode_Config3=1, Input_Buffer_Mode_Config4=1, Ref_Voltage=1.024, Ref_Voltage_Config2=1.024, Ref_Voltage_Config3=1.024, Ref_Voltage_Config4=1.024, Sample_Rate=32086, Sample_Rate_Config2=32086, Sample_Rate_Config3=10000, Sample_Rate_Config4=10000, Start_of_Conversion=0, Vdda_Value=3.3, CY_COMPONENT_NAME=ADC_DelSig_v2_20, CY_CONTROL_FILE=<:default:>, CY_FITTER_NAME=ADC, CY_INSTANCE_SHORT_NAME=ADC, CY_MAJOR_VERSION=2, CY_MINOR_VERSION=20, CY_REMOVE=false, CY_SUPPRESS_API_GEN=false, CY_VERSION=cydsfit No Version Information Found, INSTANCE_NAME=ADC, )
module ADC_DelSig_v2_20_0 (vplus, vminus, soc, eoc, aclk, nVref);
    inout   vplus;
    electrical   vplus;
    inout   vminus;
    electrical   vminus;
    input   soc;
    output  eoc;
    input   aclk;
    inout   nVref;
    electrical   nVref;


    wire  aclock;
    wire [3:0] mod_dat;
    wire  mod_reset;
    wire  Net_370;
    electrical  Net_333;
    electrical  Net_348;
    wire  Net_372;
    wire [7:0] Net_436;
    wire  Net_437;
    wire  Net_485;
    wire  Net_486;
    wire [7:0] Net_621;
    wire  Net_622;
    electrical  Net_680;
    electrical  Net_682;
    electrical  Net_687;
    electrical  Net_690;
    electrical  Net_686;
    electrical  Net_681;
    electrical  Net_677;
    electrical  Net_570;
    electrical  Net_573;
    electrical  Net_580;
    wire  Net_488;
    wire  Net_487;
    wire  Net_482;
    wire  Net_481;
    wire  Net_478;
    wire  Net_438;
    wire [3:0] Net_471;
    wire [3:0] Net_470;
    electrical  Net_352;
    electrical  Net_349;
    electrical  Net_257;
    electrical  Net_520;
    wire  Net_40;

    cy_analog_noconnect_v1_0 cy_analog_noconnect_2 (
        .noconnect(Net_349));


	cy_clock_v1_0
		#(.id("a07408f4-09d7-40d3-80f1-9b488a6077a4/b7604721-db56-4477-98c2-8fae77869066"),
		  .source_clock_id(""),
		  .divisor(0),
		  .period("83333333.3333333"),
		  .is_direct(0),
		  .is_digital(1))
		Ext_CP_Clk
		 (.clock_out(Net_487));


    cy_analog_noconnect_v1_0 cy_analog_noconnect_3 (
        .noconnect(Net_257));

	wire [0:0] tmpOE__Bypass_P03_net;
	wire [0:0] tmpFB_0__Bypass_P03_net;
	wire [0:0] tmpIO_0__Bypass_P03_net;
	wire [0:0] tmpINTERRUPT_0__Bypass_P03_net;
	electrical [0:0] tmpSIOVREF__Bypass_P03_net;

	cy_psoc3_pins_v1_10
		#(.id("a07408f4-09d7-40d3-80f1-9b488a6077a4/20681f4c-d171-47ae-a1cb-d832cd711191"),
		  .drive_mode(3'b000),
		  .ibuf_enabled(1'b0),
		  .init_dr_st(1'b0),
		  .input_sync(1'b1),
		  .intr_mode(2'b00),
		  .io_voltage(""),
		  .layout_mode("NONCONTIGUOUS"),
		  .oe_conn(1'b0),
		  .output_conn(1'b0),
		  .output_sync(1'b0),
		  .pin_aliases(""),
		  .pin_mode("A"),
		  .por_state(4),
		  .use_annotation(1'b0),
		  .sio_group_cnt(0),
		  .sio_hyst(1'b0),
		  .sio_ibuf(""),
		  .sio_info(2'b00),
		  .sio_obuf(""),
		  .sio_refsel(""),
		  .sio_vtrip(""),
		  .slew_rate(1'b0),
		  .spanning(1),
		  .vtrip(2'b10),
		  .width(1))
		Bypass_P03
		 (.oe(tmpOE__Bypass_P03_net),
		  .y({1'b0}),
		  .fb({tmpFB_0__Bypass_P03_net[0:0]}),
		  .analog({Net_348}),
		  .io({tmpIO_0__Bypass_P03_net[0:0]}),
		  .siovref(tmpSIOVREF__Bypass_P03_net),
		  .interrupt({tmpINTERRUPT_0__Bypass_P03_net[0:0]}));

	assign tmpOE__Bypass_P03_net = (`CYDEV_CHIP_MEMBER_USED == `CYDEV_CHIP_MEMBER_3A && `CYDEV_CHIP_REVISION_USED < `CYDEV_CHIP_REVISION_3A_ES3) ? ~{1'b1} : {1'b1};

	// cy_analog_virtualmux_3 (cy_analog_virtualmux_v1_0)
	cy_connect_v1_0 cy_analog_virtualmux_3_connect(Net_573, Net_257);
	defparam cy_analog_virtualmux_3_connect.sig_width = 1;

	// cy_analog_virtualmux_2 (cy_analog_virtualmux_v1_0)
	cy_connect_v1_0 cy_analog_virtualmux_2_connect(Net_580, Net_348);
	defparam cy_analog_virtualmux_2_connect.sig_width = 1;

	// cy_analog_virtualmux_1 (cy_analog_virtualmux_v1_0)
	cy_connect_v1_0 cy_analog_virtualmux_1_connect(Net_520, vminus);
	defparam cy_analog_virtualmux_1_connect.sig_width = 1;


	cy_isr_v1_0
		#(.int_type(2'b10))
		IRQ
		 (.int_signal(eoc));


	// Clock_VirtualMux (cy_virtualmux_v1_0)
	assign Net_488 = Net_40;


	cy_clock_v1_0
		#(.id("a07408f4-09d7-40d3-80f1-9b488a6077a4/edd15f43-b66b-457b-be3a-5342345270c8"),
		  .source_clock_id(""),
		  .divisor(0),
		  .period("166666666.666667"),
		  .is_direct(0),
		  .is_digital(0))
		theACLK
		 (.clock_out(Net_40));


    ZeroTerminal ZeroTerminal_2 (
        .z(Net_482));

    ZeroTerminal ZeroTerminal_1 (
        .z(Net_481));

    cy_psoc3_decimator_v1_0 DEC (
        .aclock(aclock),
        .mod_dat(mod_dat[3:0]),
        .ext_start(soc),
        .mod_reset(mod_reset),
        .interrupt(eoc));

	// cy_analog_virtualmux_5 (cy_analog_virtualmux_v1_0)
	cy_connect_v1_0 cy_analog_virtualmux_5_connect(Net_570, Net_352);
	defparam cy_analog_virtualmux_5_connect.sig_width = 1;

    cy_analog_noconnect_v1_0 cy_analog_noconnect_5 (
        .noconnect(Net_352));

    cy_psoc3_ds_mod_v4_0 DSM4 (
        .vplus(vplus),
        .vminus(Net_520),
        .modbit(Net_485),
        .reset_udb(Net_486),
        .aclock(Net_488),
        .mod_dat(Net_471[3:0]),
        .dout_udb(Net_621[7:0]),
        .reset_dec(mod_reset),
        .dec_clock(Net_478),
        .extclk_cp_udb(Net_487),
        .clk_udb(1'b0),
        .ext_pin_1(Net_580),
        .ext_pin_2(Net_573),
        .ext_vssa(Net_570),
        .qtz_ref(Net_677));
    defparam DSM4.resolution = 14;

    ZeroTerminal ZeroTerminal_3 (
        .z(Net_485));

    ZeroTerminal ZeroTerminal_5 (
        .z(Net_486));

	// Clock_VirtualMux_2 (cy_virtualmux_v1_0)
	assign mod_dat[3:0] = Net_471[3:0];

	// Clock_VirtualMux_3 (cy_virtualmux_v1_0)
	assign aclock = Net_478;

    cy_analog_noconnect_v1_0 cy_analog_noconnect_1 (
        .noconnect(Net_680));

	// cy_analog_virtualmux_4 (cy_analog_virtualmux_v1_0)
	cy_connect_v1_0 cy_analog_virtualmux_4_connect(Net_677, Net_680);
	defparam cy_analog_virtualmux_4_connect.sig_width = 1;

	// cy_analog_virtualmux_6 (cy_analog_virtualmux_v1_0)
	cy_connect_v1_0 cy_analog_virtualmux_6_connect(Net_690, Net_687);
	defparam cy_analog_virtualmux_6_connect.sig_width = 1;



endmodule

// Filter_v2_0(ChannelEnableA=true, ChannelEnableB=true, ChannelSettingsA=<enabled=true>\r\n<sample_rate=16.034>\r\n<width=WIDTH_16>\r\n<signal=INTERRUPT>\r\n<stage_count=1>\r\n<stage0=\r\n    <design_type=FIR>\r\n    <pass_type=LOW_PASS>\r\n    <window_type=BLACKMAN>\r\n    <tap_count=64>\r\n    <primary_freq=2>\r\n    <bandwidth=0.4>\r\n>\r\n<stage1=\r\n    <design_type=FIR>\r\n    <pass_type=LOW_PASS>\r\n    <window_type=BLACKMAN>\r\n    <tap_count=32>\r\n    <primary_freq=5>\r\n    <bandwidth=10>\r\n>\r\n<stage2=\r\n    <design_type=FIR>\r\n    <pass_type=LOW_PASS>\r\n    <window_type=RECTANGULAR>\r\n    <tap_count=16>\r\n    <primary_freq=15>\r\n    <bandwidth=10>\r\n>\r\n<stage3=\r\n    <design_type=FIR>\r\n    <pass_type=LOW_PASS>\r\n    <window_type=RECTANGULAR>\r\n    <tap_count=16>\r\n    <primary_freq=15>\r\n    <bandwidth=10>\r\n>\r\n, ChannelSettingsB=<enabled=true>\r\n<sample_rate=16.034>\r\n<width=WIDTH_16>\r\n<signal=INTERRUPT>\r\n<stage_count=1>\r\n<stage0=\r\n    <design_type=FIR>\r\n    <pass_type=LOW_PASS>\r\n    <window_type=BLACKMAN>\r\n    <tap_count=64>\r\n    <primary_freq=2>\r\n    <bandwidth=0.4>\r\n>\r\n<stage1=\r\n    <design_type=FIR>\r\n    <pass_type=LOW_PASS>\r\n    <window_type=RECTANGULAR>\r\n    <tap_count=32>\r\n    <primary_freq=3>\r\n    <bandwidth=10>\r\n>\r\n<stage2=\r\n    <design_type=FIR>\r\n    <pass_type=LOW_PASS>\r\n    <window_type=RECTANGULAR>\r\n    <tap_count=16>\r\n    <primary_freq=15>\r\n    <bandwidth=10>\r\n>\r\n<stage3=\r\n    <design_type=FIR>\r\n    <pass_type=LOW_PASS>\r\n    <window_type=RECTANGULAR>\r\n    <tap_count=16>\r\n    <primary_freq=15>\r\n    <bandwidth=10>\r\n>\r\n, ChannelTypeA=1, ChannelTypeB=1, CoefficientEntryEnableA=false, CoefficientEntryEnableB=false, DisplaySettingsA=2, DisplaySettingsB=2, DmaEnableA=false, DmaEnableB=false, IrqEnableA=true, IrqEnableB=true, MinBusClockVal=2.6, CY_COMPONENT_NAME=Filter_v2_0, CY_CONTROL_FILE=<:default:>, CY_FITTER_NAME=Filter, CY_INSTANCE_SHORT_NAME=Filter, CY_MAJOR_VERSION=2, CY_MINOR_VERSION=0, CY_REMOVE=false, CY_SUPPRESS_API_GEN=false, CY_VERSION=cydsfit No Version Information Found, INSTANCE_NAME=Filter, )
module Filter_v2_0_1 (DMA_Req_A, DMA_Req_B, Interrupt);
    output  DMA_Req_A;
    output  DMA_Req_B;
    output  Interrupt;


    wire  Net_1;
    wire  Net_4;
    wire  Net_8;
    wire  Net_9;
    wire  Net_5;

    ZeroTerminal ZeroTerminal_1 (
        .z(Net_1));

    cy_psoc3_dfb_v1_0 DFB (
        .in_1(Net_4),
        .out_1(Net_8),
        .out_2(Net_9),
        .interrupt(Interrupt),
        .in_2(Net_5),
        .clock(Net_1),
        .dmareq_1(DMA_Req_A),
        .dmareq_2(DMA_Req_B));

    ZeroTerminal ZeroTerminal_4 (
        .z(Net_5));

    ZeroTerminal ZeroTerminal_5 (
        .z(Net_4));



endmodule

// VDAC8_v1_70(Data_Source=0, Initial_Value=100, Strobe_Mode=0, UseWorkaround=false, VDAC_Range=0, VDAC_Speed=0, Voltage=255, CY_COMPONENT_NAME=VDAC8_v1_70, CY_CONTROL_FILE=<:default:>, CY_FITTER_NAME=VDAC, CY_INSTANCE_SHORT_NAME=VDAC, CY_MAJOR_VERSION=1, CY_MINOR_VERSION=70, CY_REMOVE=false, CY_SUPPRESS_API_GEN=false, CY_VERSION=cydsfit No Version Information Found, INSTANCE_NAME=VDAC, )
module VDAC8_v1_70_2 (strobe, data, vOut);
    input   strobe;
    input  [7:0] data;
    inout   vOut;
    electrical   vOut;

    parameter Data_Source = 0;
    parameter Initial_Value = 100;
    parameter Strobe_Mode = 0;

    electrical  Net_77;
    wire  Net_83;
    wire  Net_82;
    wire  Net_81;

    cy_psoc3_vidac8_v1_0 viDAC8 (
        .reset(Net_83),
        .idir(Net_81),
        .data(data[7:0]),
        .strobe(strobe),
        .vout(vOut),
        .iout(Net_77),
        .ioff(Net_82),
        .strobe_udb(strobe));
    defparam viDAC8.is_all_if_any = 0;
    defparam viDAC8.reg_data = 0;

    ZeroTerminal ZeroTerminal_1 (
        .z(Net_81));

    ZeroTerminal ZeroTerminal_2 (
        .z(Net_82));

    ZeroTerminal ZeroTerminal_3 (
        .z(Net_83));

    cy_analog_noconnect_v1_0 cy_analog_noconnect_1 (
        .noconnect(Net_77));



endmodule

// Component: IQ_Generator
`ifdef CY_BLK_DIR
`undef CY_BLK_DIR
`endif

`ifdef WARP
`define CY_BLK_DIR "..\IQ_Generator"
`include "..\IQ_Generator\IQ_Generator.v"
`else
`define CY_BLK_DIR "C:\Users\Simple Server\Documents\My Dropbox\SimpleServer\Projects\Simple Circuits\SimpleSDR\SimpleSDR_Receiver\SimpleSDR_PSoC\SimpleSDR_PSoC.cydsn\IQ_Generator"
`include "C:\Users\Simple Server\Documents\My Dropbox\SimpleServer\Projects\Simple Circuits\SimpleSDR\SimpleSDR_Receiver\SimpleSDR_PSoC\SimpleSDR_PSoC.cydsn\IQ_Generator\IQ_Generator.v"
`endif

// Component: FracN
`ifdef CY_BLK_DIR
`undef CY_BLK_DIR
`endif

`ifdef WARP
`define CY_BLK_DIR "..\FracN"
`include "..\FracN\FracN.v"
`else
`define CY_BLK_DIR "C:\Users\Simple Server\Documents\My Dropbox\SimpleServer\Projects\Simple Circuits\SimpleSDR\SimpleSDR_Receiver\SimpleSDR_PSoC\SimpleSDR_PSoC.cydsn\FracN"
`include "C:\Users\Simple Server\Documents\My Dropbox\SimpleServer\Projects\Simple Circuits\SimpleSDR\SimpleSDR_Receiver\SimpleSDR_PSoC\SimpleSDR_PSoC.cydsn\FracN\FracN.v"
`endif

// Component: AMuxHw_v1_50
`ifdef CY_BLK_DIR
`undef CY_BLK_DIR
`endif

`ifdef WARP
`define CY_BLK_DIR "$CYPRESS_DIR\..\psoc\content\cycomponentlibrary\CyComponentLibrary.cylib\AMuxHw_v1_50"
`include "$CYPRESS_DIR\..\psoc\content\cycomponentlibrary\CyComponentLibrary.cylib\AMuxHw_v1_50\AMuxHw_v1_50.v"
`else
`define CY_BLK_DIR "C:\Program Files (x86)\Cypress\PSoC Creator\2.0\PSoC Creator\psoc\content\cycomponentlibrary\CyComponentLibrary.cylib\AMuxHw_v1_50"
`include "C:\Program Files (x86)\Cypress\PSoC Creator\2.0\PSoC Creator\psoc\content\cycomponentlibrary\CyComponentLibrary.cylib\AMuxHw_v1_50\AMuxHw_v1_50.v"
`endif

// Component: CyControlReg_v1_60
`ifdef CY_BLK_DIR
`undef CY_BLK_DIR
`endif

`ifdef WARP
`define CY_BLK_DIR "$CYPRESS_DIR\..\psoc\content\cyprimitives\CyPrimitives.cylib\CyControlReg_v1_60"
`include "$CYPRESS_DIR\..\psoc\content\cyprimitives\CyPrimitives.cylib\CyControlReg_v1_60\CyControlReg_v1_60.v"
`else
`define CY_BLK_DIR "C:\Program Files (x86)\Cypress\PSoC Creator\2.0\PSoC Creator\psoc\content\cyprimitives\CyPrimitives.cylib\CyControlReg_v1_60"
`include "C:\Program Files (x86)\Cypress\PSoC Creator\2.0\PSoC Creator\psoc\content\cyprimitives\CyPrimitives.cylib\CyControlReg_v1_60\CyControlReg_v1_60.v"
`endif

// USBUART(DescChanged=0, DeviceDescriptors=, DeviceRelease=1, hid_class=false, HIDReportDescriptors=, ManufacturerString=Cypress, mon_vbus=false, num_string_descr=0, PID=32849, ProductString=SimpleSDR, rm_arb_int=false, rm_dma=false, rm_dma_1=true, rm_dma_2=true, rm_dma_3=true, rm_dma_4=true, rm_dma_5=true, rm_dma_6=true, rm_dma_7=true, rm_dma_8=false, rm_ep_isr_0=false, rm_ep_isr_1=false, rm_ep_isr_2=false, rm_ep_isr_3=false, rm_ep_isr_4=false, rm_ep_isr_5=false, rm_ep_isr_6=false, rm_ep_isr_7=false, rm_ep_isr_8=false, rm_isr=false, rm_ord_int=false, rm_sof_int=false, rm_usb_int=false, SerialString=, StringDescriptors=, VID=1204, z_hid_example=false, z_user_def_example=false, CY_COMPONENT_NAME=USBUART, CY_CONTROL_FILE=<:default:>, CY_FITTER_NAME=USBUART, CY_INSTANCE_SHORT_NAME=USBUART, CY_MAJOR_VERSION=0, CY_MINOR_VERSION=0, CY_REMOVE=false, CY_SUPPRESS_API_GEN=false, CY_VERSION=cydsfit No Version Information Found, INSTANCE_NAME=USBUART, )
module USBUART_3 (UNUSED);
    input   UNUSED;


    wire [7:0] dma_req;
    wire  Net_594;
    wire  Net_589;
    wire [8:0] ept_int;
    wire  Net_590;
    wire  Net_591;
    wire  Net_592;
    wire  Net_593;
    electrical  Net_548;
    electrical  Net_522;
    wire  Net_95;
    wire  Net_81;
    wire  Net_79;
    wire  Net_77;

    cy_psoc3_usb_v1_0 USB (
        .dp(Net_548),
        .dm(Net_522),
        .sof_int(Net_77),
        .arb_int(Net_79),
        .usb_int(Net_81),
        .ept_int(ept_int[8:0]),
        .ord_int(Net_95),
        .dma_req(dma_req[7:0]),
        .dma_termin(Net_594));


	cy_isr_v1_0
		#(.int_type(2'b10))
		sof_int
		 (.int_signal(Net_77));



	cy_isr_v1_0
		#(.int_type(2'b10))
		arb_int
		 (.int_signal(Net_79));



	cy_isr_v1_0
		#(.int_type(2'b10))
		bus_reset
		 (.int_signal(Net_81));



	cy_isr_v1_0
		#(.int_type(2'b10))
		ep_0
		 (.int_signal(ept_int[0:0]));



	cy_isr_v1_0
		#(.int_type(2'b10))
		ep_1
		 (.int_signal(ept_int[1:1]));



	cy_isr_v1_0
		#(.int_type(2'b10))
		ep_2
		 (.int_signal(ept_int[2:2]));



	cy_isr_v1_0
		#(.int_type(2'b10))
		ep_3
		 (.int_signal(ept_int[3:3]));



	cy_isr_v1_0
		#(.int_type(2'b10))
		ep_4
		 (.int_signal(ept_int[4:4]));



	cy_isr_v1_0
		#(.int_type(2'b10))
		ep_5
		 (.int_signal(ept_int[5:5]));



	cy_isr_v1_0
		#(.int_type(2'b10))
		ep_6
		 (.int_signal(ept_int[6:6]));



	cy_isr_v1_0
		#(.int_type(2'b10))
		ep_7
		 (.int_signal(ept_int[7:7]));



	cy_isr_v1_0
		#(.int_type(2'b10))
		ep_8
		 (.int_signal(ept_int[8:8]));



	cy_isr_v1_0
		#(.int_type(2'b10))
		ord_int
		 (.int_signal(Net_95));


	wire [0:0] tmpOE__dp_net;

	cy_psoc3_port_v1_0
		#(.width(1),
		  .siorefwidth(1),
		  .id("1e9b779e-c928-4a97-bdbe-089a133e5637/427d7144-a1e8-4bca-a79f-71f65bb81965"),
		  .pin_aliases("dp"),
		  .access_mode("HW_ONLY"),
		  .layout_mode("NONCONTIGUOUS"),
		  .port_mode("ANALOG"),
		  .intr_mode(2'b00),
		  .drive_mode(3'b000),
		  .por_state(0))
		dp
		 (.oe(tmpOE__dp_net),
		  .y(1'b0),
		  .analog(Net_548));

	assign tmpOE__dp_net = (`CYDEV_CHIP_MEMBER_USED == `CYDEV_CHIP_MEMBER_3A && `CYDEV_CHIP_REVISION_USED < `CYDEV_CHIP_REVISION_3A_ES3) ? 1'b1 : 1'b0;

	wire [0:0] tmpOE__dm_net;

	cy_psoc3_port_v1_0
		#(.width(1),
		  .siorefwidth(1),
		  .id("1e9b779e-c928-4a97-bdbe-089a133e5637/43f229e4-33ed-4b6c-9f8f-6d60713ebee5"),
		  .pin_aliases("dm"),
		  .access_mode("HW_ONLY"),
		  .layout_mode("NONCONTIGUOUS"),
		  .port_mode("ANALOG"),
		  .intr_mode(2'b00),
		  .drive_mode(3'b000),
		  .por_state(0))
		dm
		 (.oe(tmpOE__dm_net),
		  .y(1'b0),
		  .analog(Net_522));

	assign tmpOE__dm_net = (`CYDEV_CHIP_MEMBER_USED == `CYDEV_CHIP_MEMBER_3A && `CYDEV_CHIP_REVISION_USED < `CYDEV_CHIP_REVISION_3A_ES3) ? 1'b1 : 1'b0;



endmodule

// top
module top ;

    wire  Net_1253;
    wire  Net_1244;
    wire  Net_1243;
    wire  Net_1242;
    wire  Net_1241;
    wire  Net_1240;
    wire  Net_1239;
    wire  Net_1237;
    wire  Net_1236;
    wire  Net_1261;
    wire  Net_1162;
    wire  Net_1154;
    wire  Net_1153;
    electrical  Net_1192;
    wire  Net_1114;
    wire  Net_489;
    electrical  Net_1187;
    wire [7:0] Net_94;
    wire  Net_93;
    wire  Net_86;
    wire  Net_85;
    wire  Net_84;
    electrical  Net_1139;
    wire  Net_1138;
    wire  Net_1245;
    wire  Net_1136;
    wire  Net_1270;
    wire [1:0] Net_1235;
    electrical  Net_1191;
    electrical  Net_1189;
    electrical  Net_1167;
    wire  Net_1087;
    wire  Net_1089;

    ADC_DelSig_v2_20_0 ADC (
        .vplus(Net_1189),
        .vminus(Net_1191),
        .soc(1'b1),
        .eoc(Net_1245),
        .aclk(1'b0),
        .nVref(Net_1139));

    Filter_v2_0_1 Filter (
        .DMA_Req_A(Net_84),
        .DMA_Req_B(Net_85),
        .Interrupt(Net_86));

    VDAC8_v1_70_2 VDAC (
        .strobe(1'b0),
        .data(8'b00000000),
        .vOut(Net_1167));
    defparam VDAC.Data_Source = 0;
    defparam VDAC.Initial_Value = 100;
    defparam VDAC.Strobe_Mode = 0;

	wire [0:0] tmpOE__ICHAN_net;
	wire [0:0] tmpFB_0__ICHAN_net;
	wire [0:0] tmpIO_0__ICHAN_net;
	wire [0:0] tmpINTERRUPT_0__ICHAN_net;
	electrical [0:0] tmpSIOVREF__ICHAN_net;

	cy_psoc3_pins_v1_10
		#(.id("4FEFF826-FE73-4552-BC78-338363449A6B"),
		  .drive_mode(3'b000),
		  .ibuf_enabled(1'b0),
		  .init_dr_st(1'b0),
		  .input_sync(1'b1),
		  .intr_mode(2'b00),
		  .io_voltage(""),
		  .layout_mode("NONCONTIGUOUS"),
		  .oe_conn(1'b0),
		  .output_conn(1'b0),
		  .output_sync(1'b0),
		  .pin_aliases(""),
		  .pin_mode("A"),
		  .por_state(4),
		  .use_annotation(1'b0),
		  .sio_group_cnt(0),
		  .sio_hyst(1'b0),
		  .sio_ibuf(""),
		  .sio_info(2'b00),
		  .sio_obuf(""),
		  .sio_refsel(""),
		  .sio_vtrip(""),
		  .slew_rate(1'b0),
		  .spanning(1),
		  .vtrip(2'b10),
		  .width(1))
		ICHAN
		 (.oe(tmpOE__ICHAN_net),
		  .y({1'b0}),
		  .fb({tmpFB_0__ICHAN_net[0:0]}),
		  .analog({Net_1187}),
		  .io({tmpIO_0__ICHAN_net[0:0]}),
		  .siovref(tmpSIOVREF__ICHAN_net),
		  .interrupt({tmpINTERRUPT_0__ICHAN_net[0:0]}));

	assign tmpOE__ICHAN_net = (`CYDEV_CHIP_MEMBER_USED == `CYDEV_CHIP_MEMBER_3A && `CYDEV_CHIP_REVISION_USED < `CYDEV_CHIP_REVISION_3A_ES3) ? ~{1'b1} : {1'b1};

	wire [0:0] tmpOE__QOUT_net;
	wire [0:0] tmpFB_0__QOUT_net;
	wire [0:0] tmpIO_0__QOUT_net;
	wire [0:0] tmpINTERRUPT_0__QOUT_net;
	electrical [0:0] tmpSIOVREF__QOUT_net;

	cy_psoc3_pins_v1_10
		#(.id("53c8c215-a889-4667-bc84-bcdfed66ff88"),
		  .drive_mode(3'b000),
		  .ibuf_enabled(1'b0),
		  .init_dr_st(1'b0),
		  .input_sync(1'b1),
		  .intr_mode(2'b00),
		  .io_voltage(""),
		  .layout_mode("NONCONTIGUOUS"),
		  .oe_conn(1'b0),
		  .output_conn(1'b0),
		  .output_sync(1'b0),
		  .pin_aliases(""),
		  .pin_mode("A"),
		  .por_state(4),
		  .use_annotation(1'b0),
		  .sio_group_cnt(0),
		  .sio_hyst(1'b0),
		  .sio_ibuf(""),
		  .sio_info(2'b00),
		  .sio_obuf(""),
		  .sio_refsel(""),
		  .sio_vtrip(""),
		  .slew_rate(1'b0),
		  .spanning(1),
		  .vtrip(2'b10),
		  .width(1))
		QOUT
		 (.oe(tmpOE__QOUT_net),
		  .y({1'b0}),
		  .fb({tmpFB_0__QOUT_net[0:0]}),
		  .analog({Net_1167}),
		  .io({tmpIO_0__QOUT_net[0:0]}),
		  .siovref(tmpSIOVREF__QOUT_net),
		  .interrupt({tmpINTERRUPT_0__QOUT_net[0:0]}));

	assign tmpOE__QOUT_net = (`CYDEV_CHIP_MEMBER_USED == `CYDEV_CHIP_MEMBER_3A && `CYDEV_CHIP_REVISION_USED < `CYDEV_CHIP_REVISION_3A_ES3) ? ~{1'b1} : {1'b1};


	cy_clock_v1_0
		#(.id("ab077cd3-7842-4117-92f2-c95a51ce8311"),
		  .source_clock_id("75C2148C-3656-4d8a-846D-0CAE99AB6FF7"),
		  .divisor(0),
		  .period("0"),
		  .is_direct(1),
		  .is_digital(1))
		IQCLK
		 (.clock_out(Net_489));


	wire [0:0] tmpOE__ICLK_net;
	wire [0:0] tmpFB_0__ICLK_net;
	wire [0:0] tmpIO_0__ICLK_net;
	wire [0:0] tmpINTERRUPT_0__ICLK_net;
	electrical [0:0] tmpSIOVREF__ICLK_net;

	cy_psoc3_pins_v1_10
		#(.id("caf7d12f-e120-447e-bf2e-91a7a00ae2f2"),
		  .drive_mode(3'b110),
		  .ibuf_enabled(1'b1),
		  .init_dr_st(1'b0),
		  .input_sync(1'b1),
		  .intr_mode(2'b00),
		  .io_voltage(""),
		  .layout_mode("CONTIGUOUS"),
		  .oe_conn(1'b0),
		  .output_conn(1'b1),
		  .output_sync(1'b0),
		  .pin_aliases(""),
		  .pin_mode("O"),
		  .por_state(4),
		  .use_annotation(1'b0),
		  .sio_group_cnt(0),
		  .sio_hyst(1'b0),
		  .sio_ibuf(""),
		  .sio_info(2'b00),
		  .sio_obuf(""),
		  .sio_refsel(""),
		  .sio_vtrip(""),
		  .slew_rate(1'b0),
		  .spanning(0),
		  .vtrip(2'b10),
		  .width(1))
		ICLK
		 (.oe(tmpOE__ICLK_net),
		  .y({Net_1087}),
		  .fb({tmpFB_0__ICLK_net[0:0]}),
		  .io({tmpIO_0__ICLK_net[0:0]}),
		  .siovref(tmpSIOVREF__ICLK_net),
		  .interrupt({tmpINTERRUPT_0__ICLK_net[0:0]}));

	assign tmpOE__ICLK_net = (`CYDEV_CHIP_MEMBER_USED == `CYDEV_CHIP_MEMBER_3A && `CYDEV_CHIP_REVISION_USED < `CYDEV_CHIP_REVISION_3A_ES3) ? ~{1'b1} : {1'b1};

	wire [0:0] tmpOE__QCLK_net;
	wire [0:0] tmpFB_0__QCLK_net;
	wire [0:0] tmpIO_0__QCLK_net;
	wire [0:0] tmpINTERRUPT_0__QCLK_net;
	electrical [0:0] tmpSIOVREF__QCLK_net;

	cy_psoc3_pins_v1_10
		#(.id("6ec31fb1-dded-4bd1-80f7-dc9d12001957"),
		  .drive_mode(3'b110),
		  .ibuf_enabled(1'b1),
		  .init_dr_st(1'b0),
		  .input_sync(1'b1),
		  .intr_mode(2'b00),
		  .io_voltage(""),
		  .layout_mode("CONTIGUOUS"),
		  .oe_conn(1'b0),
		  .output_conn(1'b1),
		  .output_sync(1'b0),
		  .pin_aliases(""),
		  .pin_mode("O"),
		  .por_state(4),
		  .use_annotation(1'b0),
		  .sio_group_cnt(0),
		  .sio_hyst(1'b0),
		  .sio_ibuf(""),
		  .sio_info(2'b00),
		  .sio_obuf(""),
		  .sio_refsel(""),
		  .sio_vtrip(""),
		  .slew_rate(1'b0),
		  .spanning(0),
		  .vtrip(2'b10),
		  .width(1))
		QCLK
		 (.oe(tmpOE__QCLK_net),
		  .y({Net_1089}),
		  .fb({tmpFB_0__QCLK_net[0:0]}),
		  .io({tmpIO_0__QCLK_net[0:0]}),
		  .siovref(tmpSIOVREF__QCLK_net),
		  .interrupt({tmpINTERRUPT_0__QCLK_net[0:0]}));

	assign tmpOE__QCLK_net = (`CYDEV_CHIP_MEMBER_USED == `CYDEV_CHIP_MEMBER_3A && `CYDEV_CHIP_REVISION_USED < `CYDEV_CHIP_REVISION_3A_ES3) ? ~{1'b1} : {1'b1};

	wire [0:0] tmpOE__TP2_OUT_net;
	wire [0:0] tmpFB_0__TP2_OUT_net;
	wire [0:0] tmpIO_0__TP2_OUT_net;
	wire [0:0] tmpINTERRUPT_0__TP2_OUT_net;
	electrical [0:0] tmpSIOVREF__TP2_OUT_net;

	cy_psoc3_pins_v1_10
		#(.id("79be07c7-3043-4671-b430-b790142c4f01"),
		  .drive_mode(3'b110),
		  .ibuf_enabled(1'b1),
		  .init_dr_st(1'b0),
		  .input_sync(1'b1),
		  .intr_mode(2'b00),
		  .io_voltage(""),
		  .layout_mode("CONTIGUOUS"),
		  .oe_conn(1'b0),
		  .output_conn(1'b0),
		  .output_sync(1'b0),
		  .pin_aliases(""),
		  .pin_mode("O"),
		  .por_state(4),
		  .use_annotation(1'b0),
		  .sio_group_cnt(0),
		  .sio_hyst(1'b0),
		  .sio_ibuf(""),
		  .sio_info(2'b00),
		  .sio_obuf(""),
		  .sio_refsel(""),
		  .sio_vtrip(""),
		  .slew_rate(1'b0),
		  .spanning(0),
		  .vtrip(2'b10),
		  .width(1))
		TP2_OUT
		 (.oe(tmpOE__TP2_OUT_net),
		  .y({1'b0}),
		  .fb({tmpFB_0__TP2_OUT_net[0:0]}),
		  .io({tmpIO_0__TP2_OUT_net[0:0]}),
		  .siovref(tmpSIOVREF__TP2_OUT_net),
		  .interrupt({tmpINTERRUPT_0__TP2_OUT_net[0:0]}));

	assign tmpOE__TP2_OUT_net = (`CYDEV_CHIP_MEMBER_USED == `CYDEV_CHIP_MEMBER_3A && `CYDEV_CHIP_REVISION_USED < `CYDEV_CHIP_REVISION_3A_ES3) ? ~{1'b1} : {1'b1};

	wire [0:0] tmpOE__REDLED_net;
	wire [0:0] tmpFB_0__REDLED_net;
	wire [0:0] tmpIO_0__REDLED_net;
	wire [0:0] tmpINTERRUPT_0__REDLED_net;
	electrical [0:0] tmpSIOVREF__REDLED_net;

	cy_psoc3_pins_v1_10
		#(.id("c8dae798-ec46-4bb5-9bb1-1707828fd6e4"),
		  .drive_mode(3'b110),
		  .ibuf_enabled(1'b1),
		  .init_dr_st(1'b0),
		  .input_sync(1'b1),
		  .intr_mode(2'b00),
		  .io_voltage(""),
		  .layout_mode("CONTIGUOUS"),
		  .oe_conn(1'b0),
		  .output_conn(1'b0),
		  .output_sync(1'b1),
		  .pin_aliases(""),
		  .pin_mode("O"),
		  .por_state(4),
		  .use_annotation(1'b0),
		  .sio_group_cnt(0),
		  .sio_hyst(1'b0),
		  .sio_ibuf(""),
		  .sio_info(2'b00),
		  .sio_obuf(""),
		  .sio_refsel(""),
		  .sio_vtrip(""),
		  .slew_rate(1'b1),
		  .spanning(0),
		  .vtrip(2'b10),
		  .width(1))
		REDLED
		 (.oe(tmpOE__REDLED_net),
		  .y({1'b0}),
		  .fb({tmpFB_0__REDLED_net[0:0]}),
		  .io({tmpIO_0__REDLED_net[0:0]}),
		  .siovref(tmpSIOVREF__REDLED_net),
		  .interrupt({tmpINTERRUPT_0__REDLED_net[0:0]}));

	assign tmpOE__REDLED_net = (`CYDEV_CHIP_MEMBER_USED == `CYDEV_CHIP_MEMBER_3A && `CYDEV_CHIP_REVISION_USED < `CYDEV_CHIP_REVISION_3A_ES3) ? ~{1'b1} : {1'b1};

	wire [0:0] tmpOE__QCHAN_net;
	wire [0:0] tmpFB_0__QCHAN_net;
	wire [0:0] tmpIO_0__QCHAN_net;
	wire [0:0] tmpINTERRUPT_0__QCHAN_net;
	electrical [0:0] tmpSIOVREF__QCHAN_net;

	cy_psoc3_pins_v1_10
		#(.id("2b0838e0-b681-45fa-a365-f172b21b8e1d"),
		  .drive_mode(3'b000),
		  .ibuf_enabled(1'b0),
		  .init_dr_st(1'b0),
		  .input_sync(1'b1),
		  .intr_mode(2'b00),
		  .io_voltage(""),
		  .layout_mode("NONCONTIGUOUS"),
		  .oe_conn(1'b0),
		  .output_conn(1'b0),
		  .output_sync(1'b0),
		  .pin_aliases(""),
		  .pin_mode("A"),
		  .por_state(4),
		  .use_annotation(1'b0),
		  .sio_group_cnt(0),
		  .sio_hyst(1'b0),
		  .sio_ibuf(""),
		  .sio_info(2'b00),
		  .sio_obuf(""),
		  .sio_refsel(""),
		  .sio_vtrip(""),
		  .slew_rate(1'b0),
		  .spanning(1),
		  .vtrip(2'b10),
		  .width(1))
		QCHAN
		 (.oe(tmpOE__QCHAN_net),
		  .y({1'b0}),
		  .fb({tmpFB_0__QCHAN_net[0:0]}),
		  .analog({Net_1192}),
		  .io({tmpIO_0__QCHAN_net[0:0]}),
		  .siovref(tmpSIOVREF__QCHAN_net),
		  .interrupt({tmpINTERRUPT_0__QCHAN_net[0:0]}));

	assign tmpOE__QCHAN_net = (`CYDEV_CHIP_MEMBER_USED == `CYDEV_CHIP_MEMBER_3A && `CYDEV_CHIP_REVISION_USED < `CYDEV_CHIP_REVISION_3A_ES3) ? ~{1'b1} : {1'b1};

    IQ_Generator IQ_Generator (
        .clock(Net_489),
        .iout(Net_1087),
        .qout(Net_1089));

	wire [0:0] tmpOE__IOUT_net;
	wire [0:0] tmpFB_0__IOUT_net;
	wire [0:0] tmpIO_0__IOUT_net;
	wire [0:0] tmpINTERRUPT_0__IOUT_net;
	electrical [0:0] tmpSIOVREF__IOUT_net;

	cy_psoc3_pins_v1_10
		#(.id("cc3bcd7e-5dc0-48ea-9bf6-6aa082be1ada"),
		  .drive_mode(3'b000),
		  .ibuf_enabled(1'b0),
		  .init_dr_st(1'b0),
		  .input_sync(1'b1),
		  .intr_mode(2'b00),
		  .io_voltage(""),
		  .layout_mode("NONCONTIGUOUS"),
		  .oe_conn(1'b0),
		  .output_conn(1'b0),
		  .output_sync(1'b0),
		  .pin_aliases(""),
		  .pin_mode("A"),
		  .por_state(4),
		  .use_annotation(1'b0),
		  .sio_group_cnt(0),
		  .sio_hyst(1'b0),
		  .sio_ibuf(""),
		  .sio_info(2'b00),
		  .sio_obuf(""),
		  .sio_refsel(""),
		  .sio_vtrip(""),
		  .slew_rate(1'b0),
		  .spanning(1),
		  .vtrip(2'b10),
		  .width(1))
		IOUT
		 (.oe(tmpOE__IOUT_net),
		  .y({1'b0}),
		  .fb({tmpFB_0__IOUT_net[0:0]}),
		  .analog({Net_1167}),
		  .io({tmpIO_0__IOUT_net[0:0]}),
		  .siovref(tmpSIOVREF__IOUT_net),
		  .interrupt({tmpINTERRUPT_0__IOUT_net[0:0]}));

	assign tmpOE__IOUT_net = (`CYDEV_CHIP_MEMBER_USED == `CYDEV_CHIP_MEMBER_3A && `CYDEV_CHIP_REVISION_USED < `CYDEV_CHIP_REVISION_3A_ES3) ? ~{1'b1} : {1'b1};

	wire [0:0] tmpOE__ADCREF_net;
	wire [0:0] tmpFB_0__ADCREF_net;
	wire [0:0] tmpIO_0__ADCREF_net;
	wire [0:0] tmpINTERRUPT_0__ADCREF_net;
	electrical [0:0] tmpSIOVREF__ADCREF_net;

	cy_psoc3_pins_v1_10
		#(.id("52ffaae9-c953-445f-8c34-56eab6aea3f1"),
		  .drive_mode(3'b000),
		  .ibuf_enabled(1'b0),
		  .init_dr_st(1'b0),
		  .input_sync(1'b1),
		  .intr_mode(2'b00),
		  .io_voltage(""),
		  .layout_mode("NONCONTIGUOUS"),
		  .oe_conn(1'b0),
		  .output_conn(1'b0),
		  .output_sync(1'b0),
		  .pin_aliases(""),
		  .pin_mode("A"),
		  .por_state(4),
		  .use_annotation(1'b0),
		  .sio_group_cnt(0),
		  .sio_hyst(1'b0),
		  .sio_ibuf(""),
		  .sio_info(2'b00),
		  .sio_obuf(""),
		  .sio_refsel(""),
		  .sio_vtrip(""),
		  .slew_rate(1'b0),
		  .spanning(1),
		  .vtrip(2'b10),
		  .width(1))
		ADCREF
		 (.oe(tmpOE__ADCREF_net),
		  .y({1'b0}),
		  .fb({tmpFB_0__ADCREF_net[0:0]}),
		  .analog({Net_1191}),
		  .io({tmpIO_0__ADCREF_net[0:0]}),
		  .siovref(tmpSIOVREF__ADCREF_net),
		  .interrupt({tmpINTERRUPT_0__ADCREF_net[0:0]}));

	assign tmpOE__ADCREF_net = (`CYDEV_CHIP_MEMBER_USED == `CYDEV_CHIP_MEMBER_3A && `CYDEV_CHIP_REVISION_USED < `CYDEV_CHIP_REVISION_3A_ES3) ? ~{1'b1} : {1'b1};


	cy_dma_v1_0
		#(.drq_type(2'b00))
		DMA
		 (.drq(Net_1270),
		  .trq(1'b0),
		  .nrq(Net_1154));



	cy_clock_v1_0
		#(.id("eb71efb8-529b-420d-b45b-97d1b35b0772"),
		  .source_clock_id("46B167E3-1786-4598-8688-AACCF18668D4"),
		  .divisor(9),
		  .period("0"),
		  .is_direct(0),
		  .is_digital(1))
		Clock_FracN
		 (.clock_out(Net_1270));


    FracN FracN (
        .Clk(Net_1270),
        .CarryOut(Net_1261));

    // -- AMuxHw AMuxHw start -- ***
    
    // -- AMuxHw Primitive A --
    
    cy_psoc3_amux_v1_0 #(
        .muxin_width(2),
        .hw_control(1),
        .one_active(0),
        .init_mux_sel(2'h0),
        .api_type(2'b10))
        AMuxHw_Primitive(
        .muxin({
            Net_1192,
            Net_1187
            }),
        .hw_ctrl_en(Net_1235[1:0]),
        .vout(Net_1189)
        );
    
    // -- AMuxHw AMuxHw end -- ***

    CyControlReg_v1_60 IQMUX (
        .control_1(Net_1235[1]),
        .control_2(Net_1236),
        .control_3(Net_1237),
        .control_0(Net_1235[0]),
        .control_4(Net_1239),
        .control_5(Net_1240),
        .control_6(Net_1241),
        .control_7(Net_1242),
        .clock(1'b0),
        .reset(1'b0));
    defparam IQMUX.Bit0Mode = 0;
    defparam IQMUX.Bit1Mode = 0;
    defparam IQMUX.Bit2Mode = 0;
    defparam IQMUX.Bit3Mode = 0;
    defparam IQMUX.Bit4Mode = 0;
    defparam IQMUX.Bit5Mode = 0;
    defparam IQMUX.Bit6Mode = 0;
    defparam IQMUX.Bit7Mode = 0;
    defparam IQMUX.BitValue = 2;
    defparam IQMUX.DeviceFamily = "PSoC3";
    defparam IQMUX.ExtrReset = 0;
    defparam IQMUX.NumOutputs = 2;
    defparam IQMUX.SiliconRevision = "3  ";

    USBUART_3 USBUART (
        .UNUSED(1'b0));

	wire [0:0] tmpOE__TP14_OUT_net;
	wire [0:0] tmpFB_0__TP14_OUT_net;
	wire [0:0] tmpIO_0__TP14_OUT_net;
	wire [0:0] tmpINTERRUPT_0__TP14_OUT_net;
	electrical [0:0] tmpSIOVREF__TP14_OUT_net;

	cy_psoc3_pins_v1_10
		#(.id("ed092b9b-d398-4703-be89-cebf998501f6"),
		  .drive_mode(3'b110),
		  .ibuf_enabled(1'b1),
		  .init_dr_st(1'b0),
		  .input_sync(1'b1),
		  .intr_mode(2'b00),
		  .io_voltage(""),
		  .layout_mode("CONTIGUOUS"),
		  .oe_conn(1'b0),
		  .output_conn(1'b1),
		  .output_sync(1'b0),
		  .pin_aliases(""),
		  .pin_mode("O"),
		  .por_state(4),
		  .use_annotation(1'b0),
		  .sio_group_cnt(0),
		  .sio_hyst(1'b0),
		  .sio_ibuf(""),
		  .sio_info(2'b00),
		  .sio_obuf(""),
		  .sio_refsel(""),
		  .sio_vtrip(""),
		  .slew_rate(1'b0),
		  .spanning(0),
		  .vtrip(2'b10),
		  .width(1))
		TP14_OUT
		 (.oe(tmpOE__TP14_OUT_net),
		  .y({Net_1261}),
		  .fb({tmpFB_0__TP14_OUT_net[0:0]}),
		  .io({tmpIO_0__TP14_OUT_net[0:0]}),
		  .siovref(tmpSIOVREF__TP14_OUT_net),
		  .interrupt({tmpINTERRUPT_0__TP14_OUT_net[0:0]}));

	assign tmpOE__TP14_OUT_net = (`CYDEV_CHIP_MEMBER_USED == `CYDEV_CHIP_MEMBER_3A && `CYDEV_CHIP_REVISION_USED < `CYDEV_CHIP_REVISION_3A_ES3) ? ~{1'b1} : {1'b1};



endmodule

