#ifndef INCLUDED_CYFITTERKEIL_INC
#define INCLUDED_CYFITTERKEIL_INC
$INCLUDE (cydevicekeil.inc)
$INCLUDE (cydevicekeil_trm.inc)

; USBUART_bus_reset
USBUART_bus_reset__ES2_PATCH EQU 0
USBUART_bus_reset__INTC_CLR_EN_REG EQU CYREG_INTC_CLR_EN2
USBUART_bus_reset__INTC_CLR_PD_REG EQU CYREG_INTC_CLR_PD2
USBUART_bus_reset__INTC_MASK EQU 0x80
USBUART_bus_reset__INTC_NUMBER EQU 23
USBUART_bus_reset__INTC_PRIOR_NUM EQU 7
USBUART_bus_reset__INTC_PRIOR_REG EQU CYREG_INTC_PRIOR23
USBUART_bus_reset__INTC_SET_EN_REG EQU CYREG_INTC_SET_EN2
USBUART_bus_reset__INTC_SET_PD_REG EQU CYREG_INTC_SET_PD2
USBUART_bus_reset__INTC_VECT EQU (CYREG_INTC_VECT_MBASE+0x2E)

; USBUART_arb_int
USBUART_arb_int__ES2_PATCH EQU 0
USBUART_arb_int__INTC_CLR_EN_REG EQU CYREG_INTC_CLR_EN2
USBUART_arb_int__INTC_CLR_PD_REG EQU CYREG_INTC_CLR_PD2
USBUART_arb_int__INTC_MASK EQU 0x40
USBUART_arb_int__INTC_NUMBER EQU 22
USBUART_arb_int__INTC_PRIOR_NUM EQU 7
USBUART_arb_int__INTC_PRIOR_REG EQU CYREG_INTC_PRIOR22
USBUART_arb_int__INTC_SET_EN_REG EQU CYREG_INTC_SET_EN2
USBUART_arb_int__INTC_SET_PD_REG EQU CYREG_INTC_SET_PD2
USBUART_arb_int__INTC_VECT EQU (CYREG_INTC_VECT_MBASE+0x2C)

; USBUART_ord_int
USBUART_ord_int__ES2_PATCH EQU 0
USBUART_ord_int__INTC_CLR_EN_REG EQU CYREG_INTC_CLR_EN3
USBUART_ord_int__INTC_CLR_PD_REG EQU CYREG_INTC_CLR_PD3
USBUART_ord_int__INTC_MASK EQU 0x02
USBUART_ord_int__INTC_NUMBER EQU 25
USBUART_ord_int__INTC_PRIOR_NUM EQU 7
USBUART_ord_int__INTC_PRIOR_REG EQU CYREG_INTC_PRIOR25
USBUART_ord_int__INTC_SET_EN_REG EQU CYREG_INTC_SET_EN3
USBUART_ord_int__INTC_SET_PD_REG EQU CYREG_INTC_SET_PD3
USBUART_ord_int__INTC_VECT EQU (CYREG_INTC_VECT_MBASE+0x32)

; USBUART_sof_int
USBUART_sof_int__ES2_PATCH EQU 0
USBUART_sof_int__INTC_CLR_EN_REG EQU CYREG_INTC_CLR_EN2
USBUART_sof_int__INTC_CLR_PD_REG EQU CYREG_INTC_CLR_PD2
USBUART_sof_int__INTC_MASK EQU 0x20
USBUART_sof_int__INTC_NUMBER EQU 21
USBUART_sof_int__INTC_PRIOR_NUM EQU 7
USBUART_sof_int__INTC_PRIOR_REG EQU CYREG_INTC_PRIOR21
USBUART_sof_int__INTC_SET_EN_REG EQU CYREG_INTC_SET_EN2
USBUART_sof_int__INTC_SET_PD_REG EQU CYREG_INTC_SET_PD2
USBUART_sof_int__INTC_VECT EQU (CYREG_INTC_VECT_MBASE+0x2A)

; ADC_Bypass_P03
ADC_Bypass_P03__0__MASK EQU 0x08
ADC_Bypass_P03__0__PC EQU CYREG_PRT0_PC3
ADC_Bypass_P03__0__PORT EQU 0
ADC_Bypass_P03__0__SHIFT EQU 3
ADC_Bypass_P03__AG EQU CYREG_PRT0_AG
ADC_Bypass_P03__AMUX EQU CYREG_PRT0_AMUX
ADC_Bypass_P03__BIE EQU CYREG_PRT0_BIE
ADC_Bypass_P03__BIT_MASK EQU CYREG_PRT0_BIT_MASK
ADC_Bypass_P03__BYP EQU CYREG_PRT0_BYP
ADC_Bypass_P03__CTL EQU CYREG_PRT0_CTL
ADC_Bypass_P03__DM0 EQU CYREG_PRT0_DM0
ADC_Bypass_P03__DM1 EQU CYREG_PRT0_DM1
ADC_Bypass_P03__DM2 EQU CYREG_PRT0_DM2
ADC_Bypass_P03__DR EQU CYREG_PRT0_DR
ADC_Bypass_P03__INP_DIS EQU CYREG_PRT0_INP_DIS
ADC_Bypass_P03__LCD_COM_SEG EQU CYREG_PRT0_LCD_COM_SEG
ADC_Bypass_P03__LCD_EN EQU CYREG_PRT0_LCD_EN
ADC_Bypass_P03__PORT EQU 0
ADC_Bypass_P03__PRT EQU CYREG_PRT0_PRT
ADC_Bypass_P03__PRTDSI__CAPS_SEL EQU CYREG_PRT0_CAPS_SEL
ADC_Bypass_P03__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT0_DBL_SYNC_IN
ADC_Bypass_P03__PRTDSI__OE_SEL0 EQU CYREG_PRT0_OE_SEL0
ADC_Bypass_P03__PRTDSI__OE_SEL1 EQU CYREG_PRT0_OE_SEL1
ADC_Bypass_P03__PRTDSI__OUT_SEL0 EQU CYREG_PRT0_OUT_SEL0
ADC_Bypass_P03__PRTDSI__OUT_SEL1 EQU CYREG_PRT0_OUT_SEL1
ADC_Bypass_P03__PRTDSI__SYNC_OUT EQU CYREG_PRT0_SYNC_OUT
ADC_Bypass_P03__PS EQU CYREG_PRT0_PS
ADC_Bypass_P03__SLW EQU CYREG_PRT0_SLW

; ADC_Ext_CP_Clk
ADC_Ext_CP_Clk__CFG0 EQU CYREG_CLKDIST_DCFG1_CFG0
ADC_Ext_CP_Clk__CFG1 EQU CYREG_CLKDIST_DCFG1_CFG1
ADC_Ext_CP_Clk__CFG2 EQU CYREG_CLKDIST_DCFG1_CFG2
ADC_Ext_CP_Clk__CFG2_SRC_SEL_MASK EQU 0x07
ADC_Ext_CP_Clk__PM_ACT_CFG EQU CYREG_PM_ACT_CFG2
ADC_Ext_CP_Clk__PM_ACT_MSK EQU 0x02
ADC_Ext_CP_Clk__PM_STBY_CFG EQU CYREG_PM_STBY_CFG2
ADC_Ext_CP_Clk__PM_STBY_MSK EQU 0x02

; IQ_Generator
IQ_Generator_IQDividerMax__0__MASK EQU 0x01
IQ_Generator_IQDividerMax__0__POS EQU 0
IQ_Generator_IQDividerMax__16BIT_CONTROL_AUX_CTL_REG EQU CYREG_B1_UDB06_07_ACTL
IQ_Generator_IQDividerMax__16BIT_CONTROL_CONTROL_REG EQU CYREG_B1_UDB06_07_CTL
IQ_Generator_IQDividerMax__16BIT_CONTROL_COUNT_REG EQU CYREG_B1_UDB06_07_CTL
IQ_Generator_IQDividerMax__16BIT_COUNT_CONTROL_REG EQU CYREG_B1_UDB06_07_CTL
IQ_Generator_IQDividerMax__16BIT_COUNT_COUNT_REG EQU CYREG_B1_UDB06_07_CTL
IQ_Generator_IQDividerMax__16BIT_MASK_MASK_REG EQU CYREG_B1_UDB06_07_MSK
IQ_Generator_IQDividerMax__16BIT_MASK_PERIOD_REG EQU CYREG_B1_UDB06_07_MSK
IQ_Generator_IQDividerMax__16BIT_PERIOD_MASK_REG EQU CYREG_B1_UDB06_07_MSK
IQ_Generator_IQDividerMax__16BIT_PERIOD_PERIOD_REG EQU CYREG_B1_UDB06_07_MSK
IQ_Generator_IQDividerMax__1__MASK EQU 0x02
IQ_Generator_IQDividerMax__1__POS EQU 1
IQ_Generator_IQDividerMax__2__MASK EQU 0x04
IQ_Generator_IQDividerMax__2__POS EQU 2
IQ_Generator_IQDividerMax__3__MASK EQU 0x08
IQ_Generator_IQDividerMax__3__POS EQU 3
IQ_Generator_IQDividerMax__CONTROL_AUX_CTL_REG EQU CYREG_B1_UDB06_ACTL
IQ_Generator_IQDividerMax__CONTROL_REG EQU CYREG_B1_UDB06_CTL
IQ_Generator_IQDividerMax__CONTROL_ST_REG EQU CYREG_B1_UDB06_ST_CTL
IQ_Generator_IQDividerMax__COUNT_REG EQU CYREG_B1_UDB06_CTL
IQ_Generator_IQDividerMax__COUNT_ST_REG EQU CYREG_B1_UDB06_ST_CTL
IQ_Generator_IQDividerMax__MASK EQU 0x0F
IQ_Generator_IQDividerMax__MASK_CTL_AUX_CTL_REG EQU CYREG_B1_UDB06_MSK_ACTL
IQ_Generator_IQDividerMax__PERIOD_REG EQU CYREG_B1_UDB06_MSK
IQ_Generator_IQDividerMax__PER_CTL_AUX_CTL_REG EQU CYREG_B1_UDB06_MSK_ACTL

; USBUART_ep_0
USBUART_ep_0__ES2_PATCH EQU 0
USBUART_ep_0__INTC_CLR_EN_REG EQU CYREG_INTC_CLR_EN3
USBUART_ep_0__INTC_CLR_PD_REG EQU CYREG_INTC_CLR_PD3
USBUART_ep_0__INTC_MASK EQU 0x01
USBUART_ep_0__INTC_NUMBER EQU 24
USBUART_ep_0__INTC_PRIOR_NUM EQU 7
USBUART_ep_0__INTC_PRIOR_REG EQU CYREG_INTC_PRIOR24
USBUART_ep_0__INTC_SET_EN_REG EQU CYREG_INTC_SET_EN3
USBUART_ep_0__INTC_SET_PD_REG EQU CYREG_INTC_SET_PD3
USBUART_ep_0__INTC_VECT EQU (CYREG_INTC_VECT_MBASE+0x30)

; USBUART_ep_1
USBUART_ep_1__ES2_PATCH EQU 0
USBUART_ep_1__INTC_CLR_EN_REG EQU CYREG_INTC_CLR_EN0
USBUART_ep_1__INTC_CLR_PD_REG EQU CYREG_INTC_CLR_PD0
USBUART_ep_1__INTC_MASK EQU 0x02
USBUART_ep_1__INTC_NUMBER EQU 1
USBUART_ep_1__INTC_PRIOR_NUM EQU 7
USBUART_ep_1__INTC_PRIOR_REG EQU CYREG_INTC_PRIOR1
USBUART_ep_1__INTC_SET_EN_REG EQU CYREG_INTC_SET_EN0
USBUART_ep_1__INTC_SET_PD_REG EQU CYREG_INTC_SET_PD0
USBUART_ep_1__INTC_VECT EQU (CYREG_INTC_VECT_MBASE+0x02)

; USBUART_ep_2
USBUART_ep_2__ES2_PATCH EQU 0
USBUART_ep_2__INTC_CLR_EN_REG EQU CYREG_INTC_CLR_EN0
USBUART_ep_2__INTC_CLR_PD_REG EQU CYREG_INTC_CLR_PD0
USBUART_ep_2__INTC_MASK EQU 0x04
USBUART_ep_2__INTC_NUMBER EQU 2
USBUART_ep_2__INTC_PRIOR_NUM EQU 7
USBUART_ep_2__INTC_PRIOR_REG EQU CYREG_INTC_PRIOR2
USBUART_ep_2__INTC_SET_EN_REG EQU CYREG_INTC_SET_EN0
USBUART_ep_2__INTC_SET_PD_REG EQU CYREG_INTC_SET_PD0
USBUART_ep_2__INTC_VECT EQU (CYREG_INTC_VECT_MBASE+0x04)

; USBUART_ep_3
USBUART_ep_3__ES2_PATCH EQU 0
USBUART_ep_3__INTC_CLR_EN_REG EQU CYREG_INTC_CLR_EN2
USBUART_ep_3__INTC_CLR_PD_REG EQU CYREG_INTC_CLR_PD2
USBUART_ep_3__INTC_MASK EQU 0x10
USBUART_ep_3__INTC_NUMBER EQU 20
USBUART_ep_3__INTC_PRIOR_NUM EQU 7
USBUART_ep_3__INTC_PRIOR_REG EQU CYREG_INTC_PRIOR20
USBUART_ep_3__INTC_SET_EN_REG EQU CYREG_INTC_SET_EN2
USBUART_ep_3__INTC_SET_PD_REG EQU CYREG_INTC_SET_PD2
USBUART_ep_3__INTC_VECT EQU (CYREG_INTC_VECT_MBASE+0x28)

; USBUART_ep_4
USBUART_ep_4__ES2_PATCH EQU 0
USBUART_ep_4__INTC_CLR_EN_REG EQU CYREG_INTC_CLR_EN1
USBUART_ep_4__INTC_CLR_PD_REG EQU CYREG_INTC_CLR_PD1
USBUART_ep_4__INTC_MASK EQU 0x80
USBUART_ep_4__INTC_NUMBER EQU 15
USBUART_ep_4__INTC_PRIOR_NUM EQU 7
USBUART_ep_4__INTC_PRIOR_REG EQU CYREG_INTC_PRIOR15
USBUART_ep_4__INTC_SET_EN_REG EQU CYREG_INTC_SET_EN1
USBUART_ep_4__INTC_SET_PD_REG EQU CYREG_INTC_SET_PD1
USBUART_ep_4__INTC_VECT EQU (CYREG_INTC_VECT_MBASE+0x1E)

; USBUART_ep_5
USBUART_ep_5__ES2_PATCH EQU 0
USBUART_ep_5__INTC_CLR_EN_REG EQU CYREG_INTC_CLR_EN1
USBUART_ep_5__INTC_CLR_PD_REG EQU CYREG_INTC_CLR_PD1
USBUART_ep_5__INTC_MASK EQU 0x20
USBUART_ep_5__INTC_NUMBER EQU 13
USBUART_ep_5__INTC_PRIOR_NUM EQU 7
USBUART_ep_5__INTC_PRIOR_REG EQU CYREG_INTC_PRIOR13
USBUART_ep_5__INTC_SET_EN_REG EQU CYREG_INTC_SET_EN1
USBUART_ep_5__INTC_SET_PD_REG EQU CYREG_INTC_SET_PD1
USBUART_ep_5__INTC_VECT EQU (CYREG_INTC_VECT_MBASE+0x1A)

; USBUART_ep_6
USBUART_ep_6__ES2_PATCH EQU 0
USBUART_ep_6__INTC_CLR_EN_REG EQU CYREG_INTC_CLR_EN1
USBUART_ep_6__INTC_CLR_PD_REG EQU CYREG_INTC_CLR_PD1
USBUART_ep_6__INTC_MASK EQU 0x10
USBUART_ep_6__INTC_NUMBER EQU 12
USBUART_ep_6__INTC_PRIOR_NUM EQU 7
USBUART_ep_6__INTC_PRIOR_REG EQU CYREG_INTC_PRIOR12
USBUART_ep_6__INTC_SET_EN_REG EQU CYREG_INTC_SET_EN1
USBUART_ep_6__INTC_SET_PD_REG EQU CYREG_INTC_SET_PD1
USBUART_ep_6__INTC_VECT EQU (CYREG_INTC_VECT_MBASE+0x18)

; USBUART_ep_7
USBUART_ep_7__ES2_PATCH EQU 0
USBUART_ep_7__INTC_CLR_EN_REG EQU CYREG_INTC_CLR_EN0
USBUART_ep_7__INTC_CLR_PD_REG EQU CYREG_INTC_CLR_PD0
USBUART_ep_7__INTC_MASK EQU 0x01
USBUART_ep_7__INTC_NUMBER EQU 0
USBUART_ep_7__INTC_PRIOR_NUM EQU 7
USBUART_ep_7__INTC_PRIOR_REG EQU CYREG_INTC_PRIOR0
USBUART_ep_7__INTC_SET_EN_REG EQU CYREG_INTC_SET_EN0
USBUART_ep_7__INTC_SET_PD_REG EQU CYREG_INTC_SET_PD0
USBUART_ep_7__INTC_VECT EQU (CYREG_INTC_VECT_MBASE+0x00)

; USBUART_ep_8
USBUART_ep_8__ES2_PATCH EQU 0
USBUART_ep_8__INTC_CLR_EN_REG EQU CYREG_INTC_CLR_EN2
USBUART_ep_8__INTC_CLR_PD_REG EQU CYREG_INTC_CLR_PD2
USBUART_ep_8__INTC_MASK EQU 0x01
USBUART_ep_8__INTC_NUMBER EQU 16
USBUART_ep_8__INTC_PRIOR_NUM EQU 7
USBUART_ep_8__INTC_PRIOR_REG EQU CYREG_INTC_PRIOR16
USBUART_ep_8__INTC_SET_EN_REG EQU CYREG_INTC_SET_EN2
USBUART_ep_8__INTC_SET_PD_REG EQU CYREG_INTC_SET_PD2
USBUART_ep_8__INTC_VECT EQU (CYREG_INTC_VECT_MBASE+0x20)

; ADC_theACLK
ADC_theACLK__CFG0 EQU CYREG_CLKDIST_ACFG0_CFG0
ADC_theACLK__CFG1 EQU CYREG_CLKDIST_ACFG0_CFG1
ADC_theACLK__CFG2 EQU CYREG_CLKDIST_ACFG0_CFG2
ADC_theACLK__CFG2_SRC_SEL_MASK EQU 0x07
ADC_theACLK__CFG3 EQU CYREG_CLKDIST_ACFG0_CFG3
ADC_theACLK__CFG3_PHASE_DLY_MASK EQU 0x0F
ADC_theACLK__PM_ACT_CFG EQU CYREG_PM_ACT_CFG1
ADC_theACLK__PM_ACT_MSK EQU 0x01
ADC_theACLK__PM_STBY_CFG EQU CYREG_PM_STBY_CFG1
ADC_theACLK__PM_STBY_MSK EQU 0x01

; Clock_FracN
Clock_FracN__CFG0 EQU CYREG_CLKDIST_DCFG0_CFG0
Clock_FracN__CFG1 EQU CYREG_CLKDIST_DCFG0_CFG1
Clock_FracN__CFG2 EQU CYREG_CLKDIST_DCFG0_CFG2
Clock_FracN__CFG2_SRC_SEL_MASK EQU 0x07
Clock_FracN__PM_ACT_CFG EQU CYREG_PM_ACT_CFG2
Clock_FracN__PM_ACT_MSK EQU 0x01
Clock_FracN__PM_STBY_CFG EQU CYREG_PM_STBY_CFG2
Clock_FracN__PM_STBY_MSK EQU 0x01

; USBUART_USB
USBUART_USB__ARB_CFG EQU CYREG_USB_ARB_CFG
USBUART_USB__ARB_EP1_CFG EQU CYREG_USB_ARB_EP1_CFG
USBUART_USB__ARB_EP1_INT_EN EQU CYREG_USB_ARB_EP1_INT_EN
USBUART_USB__ARB_EP1_SR EQU CYREG_USB_ARB_EP1_SR
USBUART_USB__ARB_EP2_CFG EQU CYREG_USB_ARB_EP2_CFG
USBUART_USB__ARB_EP2_INT_EN EQU CYREG_USB_ARB_EP2_INT_EN
USBUART_USB__ARB_EP2_SR EQU CYREG_USB_ARB_EP2_SR
USBUART_USB__ARB_EP3_CFG EQU CYREG_USB_ARB_EP3_CFG
USBUART_USB__ARB_EP3_INT_EN EQU CYREG_USB_ARB_EP3_INT_EN
USBUART_USB__ARB_EP3_SR EQU CYREG_USB_ARB_EP3_SR
USBUART_USB__ARB_EP4_CFG EQU CYREG_USB_ARB_EP4_CFG
USBUART_USB__ARB_EP4_INT_EN EQU CYREG_USB_ARB_EP4_INT_EN
USBUART_USB__ARB_EP4_SR EQU CYREG_USB_ARB_EP4_SR
USBUART_USB__ARB_EP5_CFG EQU CYREG_USB_ARB_EP5_CFG
USBUART_USB__ARB_EP5_INT_EN EQU CYREG_USB_ARB_EP5_INT_EN
USBUART_USB__ARB_EP5_SR EQU CYREG_USB_ARB_EP5_SR
USBUART_USB__ARB_EP6_CFG EQU CYREG_USB_ARB_EP6_CFG
USBUART_USB__ARB_EP6_INT_EN EQU CYREG_USB_ARB_EP6_INT_EN
USBUART_USB__ARB_EP6_SR EQU CYREG_USB_ARB_EP6_SR
USBUART_USB__ARB_EP7_CFG EQU CYREG_USB_ARB_EP7_CFG
USBUART_USB__ARB_EP7_INT_EN EQU CYREG_USB_ARB_EP7_INT_EN
USBUART_USB__ARB_EP7_SR EQU CYREG_USB_ARB_EP7_SR
USBUART_USB__ARB_EP8_CFG EQU CYREG_USB_ARB_EP8_CFG
USBUART_USB__ARB_EP8_INT_EN EQU CYREG_USB_ARB_EP8_INT_EN
USBUART_USB__ARB_EP8_SR EQU CYREG_USB_ARB_EP8_SR
USBUART_USB__ARB_INT_EN EQU CYREG_USB_ARB_INT_EN
USBUART_USB__ARB_INT_SR EQU CYREG_USB_ARB_INT_SR
USBUART_USB__ARB_RW1_DR EQU CYREG_USB_ARB_RW1_DR
USBUART_USB__ARB_RW1_RA EQU CYREG_USB_ARB_RW1_RA
USBUART_USB__ARB_RW1_RA_MSB EQU CYREG_USB_ARB_RW1_RA_MSB
USBUART_USB__ARB_RW1_WA EQU CYREG_USB_ARB_RW1_WA
USBUART_USB__ARB_RW1_WA_MSB EQU CYREG_USB_ARB_RW1_WA_MSB
USBUART_USB__ARB_RW2_DR EQU CYREG_USB_ARB_RW2_DR
USBUART_USB__ARB_RW2_RA EQU CYREG_USB_ARB_RW2_RA
USBUART_USB__ARB_RW2_RA_MSB EQU CYREG_USB_ARB_RW2_RA_MSB
USBUART_USB__ARB_RW2_WA EQU CYREG_USB_ARB_RW2_WA
USBUART_USB__ARB_RW2_WA_MSB EQU CYREG_USB_ARB_RW2_WA_MSB
USBUART_USB__ARB_RW3_DR EQU CYREG_USB_ARB_RW3_DR
USBUART_USB__ARB_RW3_RA EQU CYREG_USB_ARB_RW3_RA
USBUART_USB__ARB_RW3_RA_MSB EQU CYREG_USB_ARB_RW3_RA_MSB
USBUART_USB__ARB_RW3_WA EQU CYREG_USB_ARB_RW3_WA
USBUART_USB__ARB_RW3_WA_MSB EQU CYREG_USB_ARB_RW3_WA_MSB
USBUART_USB__ARB_RW4_DR EQU CYREG_USB_ARB_RW4_DR
USBUART_USB__ARB_RW4_RA EQU CYREG_USB_ARB_RW4_RA
USBUART_USB__ARB_RW4_RA_MSB EQU CYREG_USB_ARB_RW4_RA_MSB
USBUART_USB__ARB_RW4_WA EQU CYREG_USB_ARB_RW4_WA
USBUART_USB__ARB_RW4_WA_MSB EQU CYREG_USB_ARB_RW4_WA_MSB
USBUART_USB__ARB_RW5_DR EQU CYREG_USB_ARB_RW5_DR
USBUART_USB__ARB_RW5_RA EQU CYREG_USB_ARB_RW5_RA
USBUART_USB__ARB_RW5_RA_MSB EQU CYREG_USB_ARB_RW5_RA_MSB
USBUART_USB__ARB_RW5_WA EQU CYREG_USB_ARB_RW5_WA
USBUART_USB__ARB_RW5_WA_MSB EQU CYREG_USB_ARB_RW5_WA_MSB
USBUART_USB__ARB_RW6_DR EQU CYREG_USB_ARB_RW6_DR
USBUART_USB__ARB_RW6_RA EQU CYREG_USB_ARB_RW6_RA
USBUART_USB__ARB_RW6_RA_MSB EQU CYREG_USB_ARB_RW6_RA_MSB
USBUART_USB__ARB_RW6_WA EQU CYREG_USB_ARB_RW6_WA
USBUART_USB__ARB_RW6_WA_MSB EQU CYREG_USB_ARB_RW6_WA_MSB
USBUART_USB__ARB_RW7_DR EQU CYREG_USB_ARB_RW7_DR
USBUART_USB__ARB_RW7_RA EQU CYREG_USB_ARB_RW7_RA
USBUART_USB__ARB_RW7_RA_MSB EQU CYREG_USB_ARB_RW7_RA_MSB
USBUART_USB__ARB_RW7_WA EQU CYREG_USB_ARB_RW7_WA
USBUART_USB__ARB_RW7_WA_MSB EQU CYREG_USB_ARB_RW7_WA_MSB
USBUART_USB__ARB_RW8_DR EQU CYREG_USB_ARB_RW8_DR
USBUART_USB__ARB_RW8_RA EQU CYREG_USB_ARB_RW8_RA
USBUART_USB__ARB_RW8_RA_MSB EQU CYREG_USB_ARB_RW8_RA_MSB
USBUART_USB__ARB_RW8_WA EQU CYREG_USB_ARB_RW8_WA
USBUART_USB__ARB_RW8_WA_MSB EQU CYREG_USB_ARB_RW8_WA_MSB
USBUART_USB__BUF_SIZE EQU CYREG_USB_BUF_SIZE
USBUART_USB__BUS_RST_CNT EQU CYREG_USB_BUS_RST_CNT
USBUART_USB__CR0 EQU CYREG_USB_CR0
USBUART_USB__CR1 EQU CYREG_USB_CR1
USBUART_USB__CWA EQU CYREG_USB_CWA
USBUART_USB__CWA_MSB EQU CYREG_USB_CWA_MSB
USBUART_USB__DMA_THRES EQU CYREG_USB_DMA_THRES
USBUART_USB__DMA_THRES_MSB EQU CYREG_USB_DMA_THRES_MSB
USBUART_USB__DYN_RECONFIG EQU CYREG_USB_DYN_RECONFIG
USBUART_USB__EP0_CNT EQU CYREG_USB_EP0_CNT
USBUART_USB__EP0_CR EQU CYREG_USB_EP0_CR
USBUART_USB__EP0_DR0 EQU CYREG_USB_EP0_DR0
USBUART_USB__EP0_DR1 EQU CYREG_USB_EP0_DR1
USBUART_USB__EP0_DR2 EQU CYREG_USB_EP0_DR2
USBUART_USB__EP0_DR3 EQU CYREG_USB_EP0_DR3
USBUART_USB__EP0_DR4 EQU CYREG_USB_EP0_DR4
USBUART_USB__EP0_DR5 EQU CYREG_USB_EP0_DR5
USBUART_USB__EP0_DR6 EQU CYREG_USB_EP0_DR6
USBUART_USB__EP0_DR7 EQU CYREG_USB_EP0_DR7
USBUART_USB__EP_ACTIVE EQU CYREG_USB_EP_ACTIVE
USBUART_USB__EP_TYPE EQU CYREG_USB_EP_TYPE
USBUART_USB__MEM_DATA EQU CYREG_USB_MEM_DATA_MBASE
USBUART_USB__OSCLK_DR0 EQU CYREG_USB_OSCLK_DR0
USBUART_USB__OSCLK_DR1 EQU CYREG_USB_OSCLK_DR1
USBUART_USB__PM_ACT_CFG EQU CYREG_PM_ACT_CFG5
USBUART_USB__PM_ACT_MSK EQU 0x01
USBUART_USB__PM_STBY_CFG EQU CYREG_PM_STBY_CFG5
USBUART_USB__PM_STBY_MSK EQU 0x01
USBUART_USB__SIE_EP1_CNT0 EQU CYREG_USB_SIE_EP1_CNT0
USBUART_USB__SIE_EP1_CNT1 EQU CYREG_USB_SIE_EP1_CNT1
USBUART_USB__SIE_EP1_CR0 EQU CYREG_USB_SIE_EP1_CR0
USBUART_USB__SIE_EP2_CNT0 EQU CYREG_USB_SIE_EP2_CNT0
USBUART_USB__SIE_EP2_CNT1 EQU CYREG_USB_SIE_EP2_CNT1
USBUART_USB__SIE_EP2_CR0 EQU CYREG_USB_SIE_EP2_CR0
USBUART_USB__SIE_EP3_CNT0 EQU CYREG_USB_SIE_EP3_CNT0
USBUART_USB__SIE_EP3_CNT1 EQU CYREG_USB_SIE_EP3_CNT1
USBUART_USB__SIE_EP3_CR0 EQU CYREG_USB_SIE_EP3_CR0
USBUART_USB__SIE_EP4_CNT0 EQU CYREG_USB_SIE_EP4_CNT0
USBUART_USB__SIE_EP4_CNT1 EQU CYREG_USB_SIE_EP4_CNT1
USBUART_USB__SIE_EP4_CR0 EQU CYREG_USB_SIE_EP4_CR0
USBUART_USB__SIE_EP5_CNT0 EQU CYREG_USB_SIE_EP5_CNT0
USBUART_USB__SIE_EP5_CNT1 EQU CYREG_USB_SIE_EP5_CNT1
USBUART_USB__SIE_EP5_CR0 EQU CYREG_USB_SIE_EP5_CR0
USBUART_USB__SIE_EP6_CNT0 EQU CYREG_USB_SIE_EP6_CNT0
USBUART_USB__SIE_EP6_CNT1 EQU CYREG_USB_SIE_EP6_CNT1
USBUART_USB__SIE_EP6_CR0 EQU CYREG_USB_SIE_EP6_CR0
USBUART_USB__SIE_EP7_CNT0 EQU CYREG_USB_SIE_EP7_CNT0
USBUART_USB__SIE_EP7_CNT1 EQU CYREG_USB_SIE_EP7_CNT1
USBUART_USB__SIE_EP7_CR0 EQU CYREG_USB_SIE_EP7_CR0
USBUART_USB__SIE_EP8_CNT0 EQU CYREG_USB_SIE_EP8_CNT0
USBUART_USB__SIE_EP8_CNT1 EQU CYREG_USB_SIE_EP8_CNT1
USBUART_USB__SIE_EP8_CR0 EQU CYREG_USB_SIE_EP8_CR0
USBUART_USB__SIE_EP_INT_EN EQU CYREG_USB_SIE_EP_INT_EN
USBUART_USB__SIE_EP_INT_SR EQU CYREG_USB_SIE_EP_INT_SR
USBUART_USB__SOF0 EQU CYREG_USB_SOF0
USBUART_USB__SOF1 EQU CYREG_USB_SOF1
USBUART_USB__USBIO_CR0 EQU CYREG_USB_USBIO_CR0
USBUART_USB__USBIO_CR1 EQU CYREG_USB_USBIO_CR1
USBUART_USB__USBIO_CR2 EQU CYREG_USB_USBIO_CR2
USBUART_USB__USB_CLK_EN EQU CYREG_USB_USB_CLK_EN

; VDAC_viDAC8
VDAC_viDAC8__CR0 EQU CYREG_DAC2_CR0
VDAC_viDAC8__CR1 EQU CYREG_DAC2_CR1
VDAC_viDAC8__D EQU CYREG_DAC2_D
VDAC_viDAC8__PM_ACT_CFG EQU CYREG_PM_ACT_CFG8
VDAC_viDAC8__PM_ACT_MSK EQU 0x04
VDAC_viDAC8__PM_STBY_CFG EQU CYREG_PM_STBY_CFG8
VDAC_viDAC8__PM_STBY_MSK EQU 0x04
VDAC_viDAC8__STROBE EQU CYREG_DAC2_STROBE
VDAC_viDAC8__SW0 EQU CYREG_DAC2_SW0
VDAC_viDAC8__SW2 EQU CYREG_DAC2_SW2
VDAC_viDAC8__SW3 EQU CYREG_DAC2_SW3
VDAC_viDAC8__SW4 EQU CYREG_DAC2_SW4
VDAC_viDAC8__TR EQU CYREG_DAC2_TR
VDAC_viDAC8__TRIM__M1 EQU CYREG_FLSHID_CUST_TABLES_DAC2_M1
VDAC_viDAC8__TRIM__M2 EQU CYREG_FLSHID_CUST_TABLES_DAC2_M2
VDAC_viDAC8__TRIM__M3 EQU CYREG_FLSHID_CUST_TABLES_DAC2_M3
VDAC_viDAC8__TRIM__M4 EQU CYREG_FLSHID_CUST_TABLES_DAC2_M4
VDAC_viDAC8__TRIM__M5 EQU CYREG_FLSHID_CUST_TABLES_DAC2_M5
VDAC_viDAC8__TRIM__M6 EQU CYREG_FLSHID_CUST_TABLES_DAC2_M6
VDAC_viDAC8__TRIM__M7 EQU CYREG_FLSHID_CUST_TABLES_DAC2_M7
VDAC_viDAC8__TRIM__M8 EQU CYREG_FLSHID_CUST_TABLES_DAC2_M8
VDAC_viDAC8__TST EQU CYREG_DAC2_TST

; Filter_DFB
Filter_DFB__ACU_SRAM_DATA EQU CYREG_DFB0_ACU_SRAM_DATA_MBASE
Filter_DFB__COHER EQU CYREG_DFB0_COHER
Filter_DFB__CR EQU CYREG_DFB0_CR
Filter_DFB__CSA_SRAM_DATA EQU CYREG_DFB0_CSA_SRAM_DATA_MBASE
Filter_DFB__CSB_SRAM_DATA EQU CYREG_DFB0_CSB_SRAM_DATA_MBASE
Filter_DFB__DALIGN EQU CYREG_DFB0_DALIGN
Filter_DFB__DMA_CTRL EQU CYREG_DFB0_DMA_CTRL
Filter_DFB__DPA_SRAM_DATA EQU CYREG_DFB0_DPA_SRAM_DATA_MBASE
Filter_DFB__DPB_SRAM_DATA EQU CYREG_DFB0_DPB_SRAM_DATA_MBASE
Filter_DFB__DSI_CTRL EQU CYREG_DFB0_DSI_CTRL
Filter_DFB__FSM_SRAM_DATA EQU CYREG_DFB0_FSM_SRAM_DATA_MBASE
Filter_DFB__HOLDA EQU CYREG_DFB0_HOLDA
Filter_DFB__HOLDAH EQU CYREG_DFB0_HOLDAH
Filter_DFB__HOLDAM EQU CYREG_DFB0_HOLDAM
Filter_DFB__HOLDAS EQU CYREG_DFB0_HOLDAS
Filter_DFB__HOLDB EQU CYREG_DFB0_HOLDB
Filter_DFB__HOLDBH EQU CYREG_DFB0_HOLDBH
Filter_DFB__HOLDBM EQU CYREG_DFB0_HOLDBM
Filter_DFB__HOLDBS EQU CYREG_DFB0_HOLDBS
Filter_DFB__INT_CTRL EQU CYREG_DFB0_INT_CTRL
Filter_DFB__PM_ACT_CFG EQU CYREG_PM_ACT_CFG6
Filter_DFB__PM_ACT_MSK EQU 0x10
Filter_DFB__PM_STBY_CFG EQU CYREG_PM_STBY_CFG6
Filter_DFB__PM_STBY_MSK EQU 0x10
Filter_DFB__RAM_DIR EQU CYREG_DFB0_RAM_DIR
Filter_DFB__RAM_EN EQU CYREG_DFB0_RAM_EN
Filter_DFB__SEMA EQU CYREG_DFB0_SEMA
Filter_DFB__SR EQU CYREG_DFB0_SR
Filter_DFB__STAGEA EQU CYREG_DFB0_STAGEA
Filter_DFB__STAGEAH EQU CYREG_DFB0_STAGEAH
Filter_DFB__STAGEAM EQU CYREG_DFB0_STAGEAM
Filter_DFB__STAGEB EQU CYREG_DFB0_STAGEB
Filter_DFB__STAGEBH EQU CYREG_DFB0_STAGEBH
Filter_DFB__STAGEBM EQU CYREG_DFB0_STAGEBM

; USBUART_dm
USBUART_dm__0__MASK EQU 0x80
USBUART_dm__0__PC EQU CYREG_IO_PC_PRT15_7_6_PC1
USBUART_dm__0__PORT EQU 15
USBUART_dm__0__SHIFT EQU 7
USBUART_dm__AG EQU CYREG_PRT15_AG
USBUART_dm__AMUX EQU CYREG_PRT15_AMUX
USBUART_dm__BIE EQU CYREG_PRT15_BIE
USBUART_dm__BIT_MASK EQU CYREG_PRT15_BIT_MASK
USBUART_dm__BYP EQU CYREG_PRT15_BYP
USBUART_dm__CTL EQU CYREG_PRT15_CTL
USBUART_dm__DM0 EQU CYREG_PRT15_DM0
USBUART_dm__DM1 EQU CYREG_PRT15_DM1
USBUART_dm__DM2 EQU CYREG_PRT15_DM2
USBUART_dm__DR EQU CYREG_PRT15_DR
USBUART_dm__INP_DIS EQU CYREG_PRT15_INP_DIS
USBUART_dm__LCD_COM_SEG EQU CYREG_PRT15_LCD_COM_SEG
USBUART_dm__LCD_EN EQU CYREG_PRT15_LCD_EN
USBUART_dm__PORT EQU 15
USBUART_dm__PRT EQU CYREG_PRT15_PRT
USBUART_dm__PRTDSI__CAPS_SEL EQU CYREG_PRT15_CAPS_SEL
USBUART_dm__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT15_DBL_SYNC_IN
USBUART_dm__PRTDSI__OE_SEL0 EQU CYREG_PRT15_OE_SEL0
USBUART_dm__PRTDSI__OE_SEL1 EQU CYREG_PRT15_OE_SEL1
USBUART_dm__PRTDSI__OUT_SEL0 EQU CYREG_PRT15_OUT_SEL0
USBUART_dm__PRTDSI__OUT_SEL1 EQU CYREG_PRT15_OUT_SEL1
USBUART_dm__PRTDSI__SYNC_OUT EQU CYREG_PRT15_SYNC_OUT
USBUART_dm__PS EQU CYREG_PRT15_PS
USBUART_dm__SLW EQU CYREG_PRT15_SLW
USBUART_dm__dm__MASK EQU 0x80
USBUART_dm__dm__PC EQU CYREG_IO_PC_PRT15_7_6_PC1
USBUART_dm__dm__PORT EQU 15
USBUART_dm__dm__SHIFT EQU 7

; USBUART_dp
USBUART_dp__0__MASK EQU 0x40
USBUART_dp__0__PC EQU CYREG_IO_PC_PRT15_7_6_PC0
USBUART_dp__0__PORT EQU 15
USBUART_dp__0__SHIFT EQU 6
USBUART_dp__AG EQU CYREG_PRT15_AG
USBUART_dp__AMUX EQU CYREG_PRT15_AMUX
USBUART_dp__BIE EQU CYREG_PRT15_BIE
USBUART_dp__BIT_MASK EQU CYREG_PRT15_BIT_MASK
USBUART_dp__BYP EQU CYREG_PRT15_BYP
USBUART_dp__CTL EQU CYREG_PRT15_CTL
USBUART_dp__DM0 EQU CYREG_PRT15_DM0
USBUART_dp__DM1 EQU CYREG_PRT15_DM1
USBUART_dp__DM2 EQU CYREG_PRT15_DM2
USBUART_dp__DR EQU CYREG_PRT15_DR
USBUART_dp__INP_DIS EQU CYREG_PRT15_INP_DIS
USBUART_dp__LCD_COM_SEG EQU CYREG_PRT15_LCD_COM_SEG
USBUART_dp__LCD_EN EQU CYREG_PRT15_LCD_EN
USBUART_dp__PORT EQU 15
USBUART_dp__PRT EQU CYREG_PRT15_PRT
USBUART_dp__PRTDSI__CAPS_SEL EQU CYREG_PRT15_CAPS_SEL
USBUART_dp__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT15_DBL_SYNC_IN
USBUART_dp__PRTDSI__OE_SEL0 EQU CYREG_PRT15_OE_SEL0
USBUART_dp__PRTDSI__OE_SEL1 EQU CYREG_PRT15_OE_SEL1
USBUART_dp__PRTDSI__OUT_SEL0 EQU CYREG_PRT15_OUT_SEL0
USBUART_dp__PRTDSI__OUT_SEL1 EQU CYREG_PRT15_OUT_SEL1
USBUART_dp__PRTDSI__SYNC_OUT EQU CYREG_PRT15_SYNC_OUT
USBUART_dp__PS EQU CYREG_PRT15_PS
USBUART_dp__SLW EQU CYREG_PRT15_SLW
USBUART_dp__dp__MASK EQU 0x40
USBUART_dp__dp__PC EQU CYREG_IO_PC_PRT15_7_6_PC0
USBUART_dp__dp__PORT EQU 15
USBUART_dp__dp__SHIFT EQU 6

; ADC_DSM4
ADC_DSM4__BUF0 EQU CYREG_DSM0_BUF0
ADC_DSM4__BUF1 EQU CYREG_DSM0_BUF1
ADC_DSM4__BUF2 EQU CYREG_DSM0_BUF2
ADC_DSM4__BUF3 EQU CYREG_DSM0_BUF3
ADC_DSM4__CLK EQU CYREG_DSM0_CLK
ADC_DSM4__CR0 EQU CYREG_DSM0_CR0
ADC_DSM4__CR1 EQU CYREG_DSM0_CR1
ADC_DSM4__CR10 EQU CYREG_DSM0_CR10
ADC_DSM4__CR11 EQU CYREG_DSM0_CR11
ADC_DSM4__CR12 EQU CYREG_DSM0_CR12
ADC_DSM4__CR13 EQU CYREG_DSM0_CR13
ADC_DSM4__CR14 EQU CYREG_DSM0_CR14
ADC_DSM4__CR15 EQU CYREG_DSM0_CR15
ADC_DSM4__CR16 EQU CYREG_DSM0_CR16
ADC_DSM4__CR17 EQU CYREG_DSM0_CR17
ADC_DSM4__CR2 EQU CYREG_DSM0_CR2
ADC_DSM4__CR3 EQU CYREG_DSM0_CR3
ADC_DSM4__CR4 EQU CYREG_DSM0_CR4
ADC_DSM4__CR5 EQU CYREG_DSM0_CR5
ADC_DSM4__CR6 EQU CYREG_DSM0_CR6
ADC_DSM4__CR7 EQU CYREG_DSM0_CR7
ADC_DSM4__CR8 EQU CYREG_DSM0_CR8
ADC_DSM4__CR9 EQU CYREG_DSM0_CR9
ADC_DSM4__DEM0 EQU CYREG_DSM0_DEM0
ADC_DSM4__DEM1 EQU CYREG_DSM0_DEM1
ADC_DSM4__MISC EQU CYREG_DSM0_MISC
ADC_DSM4__OUT0 EQU CYREG_DSM0_OUT0
ADC_DSM4__OUT1 EQU CYREG_DSM0_OUT1
ADC_DSM4__REF0 EQU CYREG_DSM0_REF0
ADC_DSM4__REF1 EQU CYREG_DSM0_REF1
ADC_DSM4__REF2 EQU CYREG_DSM0_REF2
ADC_DSM4__REF3 EQU CYREG_DSM0_REF3
ADC_DSM4__RSVD1 EQU CYREG_DSM0_RSVD1
ADC_DSM4__SW0 EQU CYREG_DSM0_SW0
ADC_DSM4__SW2 EQU CYREG_DSM0_SW2
ADC_DSM4__SW3 EQU CYREG_DSM0_SW3
ADC_DSM4__SW4 EQU CYREG_DSM0_SW4
ADC_DSM4__SW6 EQU CYREG_DSM0_SW6
ADC_DSM4__TR0 EQU CYREG_NPUMP_DSM_TR0
ADC_DSM4__TST0 EQU CYREG_DSM0_TST0
ADC_DSM4__TST1 EQU CYREG_DSM0_TST1

; TP14_OUT
TP14_OUT__0__MASK EQU 0x10
TP14_OUT__0__PC EQU CYREG_PRT1_PC4
TP14_OUT__0__PORT EQU 1
TP14_OUT__0__SHIFT EQU 4
TP14_OUT__AG EQU CYREG_PRT1_AG
TP14_OUT__AMUX EQU CYREG_PRT1_AMUX
TP14_OUT__BIE EQU CYREG_PRT1_BIE
TP14_OUT__BIT_MASK EQU CYREG_PRT1_BIT_MASK
TP14_OUT__BYP EQU CYREG_PRT1_BYP
TP14_OUT__CTL EQU CYREG_PRT1_CTL
TP14_OUT__DM0 EQU CYREG_PRT1_DM0
TP14_OUT__DM1 EQU CYREG_PRT1_DM1
TP14_OUT__DM2 EQU CYREG_PRT1_DM2
TP14_OUT__DR EQU CYREG_PRT1_DR
TP14_OUT__INP_DIS EQU CYREG_PRT1_INP_DIS
TP14_OUT__LCD_COM_SEG EQU CYREG_PRT1_LCD_COM_SEG
TP14_OUT__LCD_EN EQU CYREG_PRT1_LCD_EN
TP14_OUT__MASK EQU 0x10
TP14_OUT__PORT EQU 1
TP14_OUT__PRT EQU CYREG_PRT1_PRT
TP14_OUT__PRTDSI__CAPS_SEL EQU CYREG_PRT1_CAPS_SEL
TP14_OUT__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT1_DBL_SYNC_IN
TP14_OUT__PRTDSI__OE_SEL0 EQU CYREG_PRT1_OE_SEL0
TP14_OUT__PRTDSI__OE_SEL1 EQU CYREG_PRT1_OE_SEL1
TP14_OUT__PRTDSI__OUT_SEL0 EQU CYREG_PRT1_OUT_SEL0
TP14_OUT__PRTDSI__OUT_SEL1 EQU CYREG_PRT1_OUT_SEL1
TP14_OUT__PRTDSI__SYNC_OUT EQU CYREG_PRT1_SYNC_OUT
TP14_OUT__PS EQU CYREG_PRT1_PS
TP14_OUT__SHIFT EQU 4
TP14_OUT__SLW EQU CYREG_PRT1_SLW

; ADC_DEC
ADC_DEC__COHER EQU CYREG_DEC_COHER
ADC_DEC__CR EQU CYREG_DEC_CR
ADC_DEC__DR1 EQU CYREG_DEC_DR1
ADC_DEC__DR2 EQU CYREG_DEC_DR2
ADC_DEC__DR2H EQU CYREG_DEC_DR2H
ADC_DEC__GCOR EQU CYREG_DEC_GCOR
ADC_DEC__GCORH EQU CYREG_DEC_GCORH
ADC_DEC__GVAL EQU CYREG_DEC_GVAL
ADC_DEC__OCOR EQU CYREG_DEC_OCOR
ADC_DEC__OCORH EQU CYREG_DEC_OCORH
ADC_DEC__OCORM EQU CYREG_DEC_OCORM
ADC_DEC__OUTSAMP EQU CYREG_DEC_OUTSAMP
ADC_DEC__OUTSAMPH EQU CYREG_DEC_OUTSAMPH
ADC_DEC__OUTSAMPM EQU CYREG_DEC_OUTSAMPM
ADC_DEC__OUTSAMPS EQU CYREG_DEC_OUTSAMPS
ADC_DEC__PM_ACT_CFG EQU CYREG_PM_ACT_CFG10
ADC_DEC__PM_ACT_MSK EQU 0x01
ADC_DEC__PM_STBY_CFG EQU CYREG_PM_STBY_CFG10
ADC_DEC__PM_STBY_MSK EQU 0x01
ADC_DEC__SHIFT1 EQU CYREG_DEC_SHIFT1
ADC_DEC__SHIFT2 EQU CYREG_DEC_SHIFT2
ADC_DEC__SR EQU CYREG_DEC_SR
ADC_DEC__TRIM__M1 EQU CYREG_FLSHID_CUST_TABLES_DEC_M1
ADC_DEC__TRIM__M2 EQU CYREG_FLSHID_CUST_TABLES_DEC_M2
ADC_DEC__TRIM__M3 EQU CYREG_FLSHID_CUST_TABLES_DEC_M3
ADC_DEC__TRIM__M4 EQU CYREG_FLSHID_CUST_TABLES_DEC_M4
ADC_DEC__TRIM__M5 EQU CYREG_FLSHID_CUST_TABLES_DEC_M5
ADC_DEC__TRIM__M6 EQU CYREG_FLSHID_CUST_TABLES_DEC_M6
ADC_DEC__TRIM__M7 EQU CYREG_FLSHID_CUST_TABLES_DEC_M7
ADC_DEC__TRIM__M8 EQU CYREG_FLSHID_CUST_TABLES_DEC_M8

; ADC_IRQ
ADC_IRQ__ES2_PATCH EQU 0
ADC_IRQ__INTC_CLR_EN_REG EQU CYREG_INTC_CLR_EN3
ADC_IRQ__INTC_CLR_PD_REG EQU CYREG_INTC_CLR_PD3
ADC_IRQ__INTC_MASK EQU 0x20
ADC_IRQ__INTC_NUMBER EQU 29
ADC_IRQ__INTC_PRIOR_NUM EQU 7
ADC_IRQ__INTC_PRIOR_REG EQU CYREG_INTC_PRIOR29
ADC_IRQ__INTC_SET_EN_REG EQU CYREG_INTC_SET_EN3
ADC_IRQ__INTC_SET_PD_REG EQU CYREG_INTC_SET_PD3
ADC_IRQ__INTC_VECT EQU (CYREG_INTC_VECT_MBASE+0x3A)

; TP2_OUT
TP2_OUT__0__MASK EQU 0x10
TP2_OUT__0__PC EQU CYREG_PRT0_PC4
TP2_OUT__0__PORT EQU 0
TP2_OUT__0__SHIFT EQU 4
TP2_OUT__AG EQU CYREG_PRT0_AG
TP2_OUT__AMUX EQU CYREG_PRT0_AMUX
TP2_OUT__BIE EQU CYREG_PRT0_BIE
TP2_OUT__BIT_MASK EQU CYREG_PRT0_BIT_MASK
TP2_OUT__BYP EQU CYREG_PRT0_BYP
TP2_OUT__CTL EQU CYREG_PRT0_CTL
TP2_OUT__DM0 EQU CYREG_PRT0_DM0
TP2_OUT__DM1 EQU CYREG_PRT0_DM1
TP2_OUT__DM2 EQU CYREG_PRT0_DM2
TP2_OUT__DR EQU CYREG_PRT0_DR
TP2_OUT__INP_DIS EQU CYREG_PRT0_INP_DIS
TP2_OUT__LCD_COM_SEG EQU CYREG_PRT0_LCD_COM_SEG
TP2_OUT__LCD_EN EQU CYREG_PRT0_LCD_EN
TP2_OUT__MASK EQU 0x10
TP2_OUT__PORT EQU 0
TP2_OUT__PRT EQU CYREG_PRT0_PRT
TP2_OUT__PRTDSI__CAPS_SEL EQU CYREG_PRT0_CAPS_SEL
TP2_OUT__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT0_DBL_SYNC_IN
TP2_OUT__PRTDSI__OE_SEL0 EQU CYREG_PRT0_OE_SEL0
TP2_OUT__PRTDSI__OE_SEL1 EQU CYREG_PRT0_OE_SEL1
TP2_OUT__PRTDSI__OUT_SEL0 EQU CYREG_PRT0_OUT_SEL0
TP2_OUT__PRTDSI__OUT_SEL1 EQU CYREG_PRT0_OUT_SEL1
TP2_OUT__PRTDSI__SYNC_OUT EQU CYREG_PRT0_SYNC_OUT
TP2_OUT__PS EQU CYREG_PRT0_PS
TP2_OUT__SHIFT EQU 4
TP2_OUT__SLW EQU CYREG_PRT0_SLW

; ADCREF
ADCREF__0__MASK EQU 0x08
ADCREF__0__PC EQU CYREG_PRT2_PC3
ADCREF__0__PORT EQU 2
ADCREF__0__SHIFT EQU 3
ADCREF__AG EQU CYREG_PRT2_AG
ADCREF__AMUX EQU CYREG_PRT2_AMUX
ADCREF__BIE EQU CYREG_PRT2_BIE
ADCREF__BIT_MASK EQU CYREG_PRT2_BIT_MASK
ADCREF__BYP EQU CYREG_PRT2_BYP
ADCREF__CTL EQU CYREG_PRT2_CTL
ADCREF__DM0 EQU CYREG_PRT2_DM0
ADCREF__DM1 EQU CYREG_PRT2_DM1
ADCREF__DM2 EQU CYREG_PRT2_DM2
ADCREF__DR EQU CYREG_PRT2_DR
ADCREF__INP_DIS EQU CYREG_PRT2_INP_DIS
ADCREF__LCD_COM_SEG EQU CYREG_PRT2_LCD_COM_SEG
ADCREF__LCD_EN EQU CYREG_PRT2_LCD_EN
ADCREF__PORT EQU 2
ADCREF__PRT EQU CYREG_PRT2_PRT
ADCREF__PRTDSI__CAPS_SEL EQU CYREG_PRT2_CAPS_SEL
ADCREF__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT2_DBL_SYNC_IN
ADCREF__PRTDSI__OE_SEL0 EQU CYREG_PRT2_OE_SEL0
ADCREF__PRTDSI__OE_SEL1 EQU CYREG_PRT2_OE_SEL1
ADCREF__PRTDSI__OUT_SEL0 EQU CYREG_PRT2_OUT_SEL0
ADCREF__PRTDSI__OUT_SEL1 EQU CYREG_PRT2_OUT_SEL1
ADCREF__PRTDSI__SYNC_OUT EQU CYREG_PRT2_SYNC_OUT
ADCREF__PS EQU CYREG_PRT2_PS
ADCREF__SLW EQU CYREG_PRT2_SLW

; REDLED
REDLED__0__MASK EQU 0x01
REDLED__0__PC EQU CYREG_PRT0_PC0
REDLED__0__PORT EQU 0
REDLED__0__SHIFT EQU 0
REDLED__AG EQU CYREG_PRT0_AG
REDLED__AMUX EQU CYREG_PRT0_AMUX
REDLED__BIE EQU CYREG_PRT0_BIE
REDLED__BIT_MASK EQU CYREG_PRT0_BIT_MASK
REDLED__BYP EQU CYREG_PRT0_BYP
REDLED__CTL EQU CYREG_PRT0_CTL
REDLED__DM0 EQU CYREG_PRT0_DM0
REDLED__DM1 EQU CYREG_PRT0_DM1
REDLED__DM2 EQU CYREG_PRT0_DM2
REDLED__DR EQU CYREG_PRT0_DR
REDLED__INP_DIS EQU CYREG_PRT0_INP_DIS
REDLED__LCD_COM_SEG EQU CYREG_PRT0_LCD_COM_SEG
REDLED__LCD_EN EQU CYREG_PRT0_LCD_EN
REDLED__MASK EQU 0x01
REDLED__PORT EQU 0
REDLED__PRT EQU CYREG_PRT0_PRT
REDLED__PRTDSI__CAPS_SEL EQU CYREG_PRT0_CAPS_SEL
REDLED__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT0_DBL_SYNC_IN
REDLED__PRTDSI__OE_SEL0 EQU CYREG_PRT0_OE_SEL0
REDLED__PRTDSI__OE_SEL1 EQU CYREG_PRT0_OE_SEL1
REDLED__PRTDSI__OUT_SEL0 EQU CYREG_PRT0_OUT_SEL0
REDLED__PRTDSI__OUT_SEL1 EQU CYREG_PRT0_OUT_SEL1
REDLED__PRTDSI__SYNC_OUT EQU CYREG_PRT0_SYNC_OUT
REDLED__PS EQU CYREG_PRT0_PS
REDLED__SHIFT EQU 0
REDLED__SLW EQU CYREG_PRT0_SLW

; FracN
FracN_FracHi__0__MASK EQU 0x01
FracN_FracHi__0__POS EQU 0
FracN_FracHi__16BIT_CONTROL_AUX_CTL_REG EQU CYREG_B0_UDB04_05_ACTL
FracN_FracHi__16BIT_CONTROL_CONTROL_REG EQU CYREG_B0_UDB04_05_CTL
FracN_FracHi__16BIT_CONTROL_COUNT_REG EQU CYREG_B0_UDB04_05_CTL
FracN_FracHi__16BIT_COUNT_CONTROL_REG EQU CYREG_B0_UDB04_05_CTL
FracN_FracHi__16BIT_COUNT_COUNT_REG EQU CYREG_B0_UDB04_05_CTL
FracN_FracHi__16BIT_MASK_MASK_REG EQU CYREG_B0_UDB04_05_MSK
FracN_FracHi__16BIT_MASK_PERIOD_REG EQU CYREG_B0_UDB04_05_MSK
FracN_FracHi__16BIT_PERIOD_MASK_REG EQU CYREG_B0_UDB04_05_MSK
FracN_FracHi__16BIT_PERIOD_PERIOD_REG EQU CYREG_B0_UDB04_05_MSK
FracN_FracHi__1__MASK EQU 0x02
FracN_FracHi__1__POS EQU 1
FracN_FracHi__2__MASK EQU 0x04
FracN_FracHi__2__POS EQU 2
FracN_FracHi__3__MASK EQU 0x08
FracN_FracHi__3__POS EQU 3
FracN_FracHi__4__MASK EQU 0x10
FracN_FracHi__4__POS EQU 4
FracN_FracHi__5__MASK EQU 0x20
FracN_FracHi__5__POS EQU 5
FracN_FracHi__7__MASK EQU 0x80
FracN_FracHi__7__POS EQU 7
FracN_FracHi__CONTROL_AUX_CTL_REG EQU CYREG_B0_UDB04_ACTL
FracN_FracHi__CONTROL_REG EQU CYREG_B0_UDB04_CTL
FracN_FracHi__CONTROL_ST_REG EQU CYREG_B0_UDB04_ST_CTL
FracN_FracHi__COUNT_REG EQU CYREG_B0_UDB04_CTL
FracN_FracHi__COUNT_ST_REG EQU CYREG_B0_UDB04_ST_CTL
FracN_FracHi__MASK EQU 0xBF
FracN_FracHi__MASK_CTL_AUX_CTL_REG EQU CYREG_B0_UDB04_MSK_ACTL
FracN_FracHi__PERIOD_REG EQU CYREG_B0_UDB04_MSK
FracN_FracHi__PER_CTL_AUX_CTL_REG EQU CYREG_B0_UDB04_MSK_ACTL
FracN_FracLo__0__MASK EQU 0x01
FracN_FracLo__0__POS EQU 0
FracN_FracLo__16BIT_CONTROL_AUX_CTL_REG EQU CYREG_B0_UDB03_04_ACTL
FracN_FracLo__16BIT_CONTROL_CONTROL_REG EQU CYREG_B0_UDB03_04_CTL
FracN_FracLo__16BIT_CONTROL_COUNT_REG EQU CYREG_B0_UDB03_04_CTL
FracN_FracLo__16BIT_COUNT_CONTROL_REG EQU CYREG_B0_UDB03_04_CTL
FracN_FracLo__16BIT_COUNT_COUNT_REG EQU CYREG_B0_UDB03_04_CTL
FracN_FracLo__16BIT_MASK_MASK_REG EQU CYREG_B0_UDB03_04_MSK
FracN_FracLo__16BIT_MASK_PERIOD_REG EQU CYREG_B0_UDB03_04_MSK
FracN_FracLo__16BIT_PERIOD_MASK_REG EQU CYREG_B0_UDB03_04_MSK
FracN_FracLo__16BIT_PERIOD_PERIOD_REG EQU CYREG_B0_UDB03_04_MSK
FracN_FracLo__1__MASK EQU 0x02
FracN_FracLo__1__POS EQU 1
FracN_FracLo__2__MASK EQU 0x04
FracN_FracLo__2__POS EQU 2
FracN_FracLo__3__MASK EQU 0x08
FracN_FracLo__3__POS EQU 3
FracN_FracLo__4__MASK EQU 0x10
FracN_FracLo__4__POS EQU 4
FracN_FracLo__5__MASK EQU 0x20
FracN_FracLo__5__POS EQU 5
FracN_FracLo__6__MASK EQU 0x40
FracN_FracLo__6__POS EQU 6
FracN_FracLo__7__MASK EQU 0x80
FracN_FracLo__7__POS EQU 7
FracN_FracLo__CONTROL_AUX_CTL_REG EQU CYREG_B0_UDB03_ACTL
FracN_FracLo__CONTROL_REG EQU CYREG_B0_UDB03_CTL
FracN_FracLo__CONTROL_ST_REG EQU CYREG_B0_UDB03_ST_CTL
FracN_FracLo__COUNT_REG EQU CYREG_B0_UDB03_CTL
FracN_FracLo__COUNT_ST_REG EQU CYREG_B0_UDB03_ST_CTL
FracN_FracLo__MASK EQU 0xFF
FracN_FracLo__MASK_CTL_AUX_CTL_REG EQU CYREG_B0_UDB03_MSK_ACTL
FracN_FracLo__PERIOD_REG EQU CYREG_B0_UDB03_MSK
FracN_FracLo__PER_CTL_AUX_CTL_REG EQU CYREG_B0_UDB03_MSK_ACTL
FracN_PLL_N__0__MASK EQU 0x01
FracN_PLL_N__0__POS EQU 0
FracN_PLL_N__16BIT_CONTROL_AUX_CTL_REG EQU CYREG_B0_UDB06_07_ACTL
FracN_PLL_N__16BIT_CONTROL_CONTROL_REG EQU CYREG_B0_UDB06_07_CTL
FracN_PLL_N__16BIT_CONTROL_COUNT_REG EQU CYREG_B0_UDB06_07_CTL
FracN_PLL_N__16BIT_COUNT_CONTROL_REG EQU CYREG_B0_UDB06_07_CTL
FracN_PLL_N__16BIT_COUNT_COUNT_REG EQU CYREG_B0_UDB06_07_CTL
FracN_PLL_N__16BIT_MASK_MASK_REG EQU CYREG_B0_UDB06_07_MSK
FracN_PLL_N__16BIT_MASK_PERIOD_REG EQU CYREG_B0_UDB06_07_MSK
FracN_PLL_N__16BIT_PERIOD_MASK_REG EQU CYREG_B0_UDB06_07_MSK
FracN_PLL_N__16BIT_PERIOD_PERIOD_REG EQU CYREG_B0_UDB06_07_MSK
FracN_PLL_N__1__MASK EQU 0x02
FracN_PLL_N__1__POS EQU 1
FracN_PLL_N__2__MASK EQU 0x04
FracN_PLL_N__2__POS EQU 2
FracN_PLL_N__3__MASK EQU 0x08
FracN_PLL_N__3__POS EQU 3
FracN_PLL_N__4__MASK EQU 0x10
FracN_PLL_N__4__POS EQU 4
FracN_PLL_N__5__MASK EQU 0x20
FracN_PLL_N__5__POS EQU 5
FracN_PLL_N__6__MASK EQU 0x40
FracN_PLL_N__6__POS EQU 6
FracN_PLL_N__CONTROL_AUX_CTL_REG EQU CYREG_B0_UDB06_ACTL
FracN_PLL_N__CONTROL_REG EQU CYREG_B0_UDB06_CTL
FracN_PLL_N__CONTROL_ST_REG EQU CYREG_B0_UDB06_ST_CTL
FracN_PLL_N__COUNT_REG EQU CYREG_B0_UDB06_CTL
FracN_PLL_N__COUNT_ST_REG EQU CYREG_B0_UDB06_ST_CTL
FracN_PLL_N__MASK EQU 0x7F
FracN_PLL_N__MASK_CTL_AUX_CTL_REG EQU CYREG_B0_UDB06_MSK_ACTL
FracN_PLL_N__PERIOD_REG EQU CYREG_B0_UDB06_MSK
FracN_PLL_N__PER_CTL_AUX_CTL_REG EQU CYREG_B0_UDB06_MSK_ACTL
FracN_PLL_P_Reg__0__MASK EQU 0x01
FracN_PLL_P_Reg__0__POS EQU 0
FracN_PLL_P_Reg__16BIT_STATUS_AUX_CTL_REG EQU CYREG_B0_UDB01_02_ACTL
FracN_PLL_P_Reg__16BIT_STATUS_REG EQU CYREG_B0_UDB01_02_ST
FracN_PLL_P_Reg__1__MASK EQU 0x02
FracN_PLL_P_Reg__1__POS EQU 1
FracN_PLL_P_Reg__2__MASK EQU 0x04
FracN_PLL_P_Reg__2__POS EQU 2
FracN_PLL_P_Reg__3__MASK EQU 0x08
FracN_PLL_P_Reg__3__POS EQU 3
FracN_PLL_P_Reg__4__MASK EQU 0x10
FracN_PLL_P_Reg__4__POS EQU 4
FracN_PLL_P_Reg__5__MASK EQU 0x20
FracN_PLL_P_Reg__5__POS EQU 5
FracN_PLL_P_Reg__6__MASK EQU 0x40
FracN_PLL_P_Reg__6__POS EQU 6
FracN_PLL_P_Reg__MASK EQU 0x7F
FracN_PLL_P_Reg__MASK_REG EQU CYREG_B0_UDB01_MSK
FracN_PLL_P_Reg__STATUS_AUX_CTL_REG EQU CYREG_B0_UDB01_ACTL
FracN_PLL_P_Reg__STATUS_REG EQU CYREG_B0_UDB01_ST

; ICHAN
ICHAN__0__MASK EQU 0x20
ICHAN__0__PC EQU CYREG_PRT2_PC5
ICHAN__0__PORT EQU 2
ICHAN__0__SHIFT EQU 5
ICHAN__AG EQU CYREG_PRT2_AG
ICHAN__AMUX EQU CYREG_PRT2_AMUX
ICHAN__BIE EQU CYREG_PRT2_BIE
ICHAN__BIT_MASK EQU CYREG_PRT2_BIT_MASK
ICHAN__BYP EQU CYREG_PRT2_BYP
ICHAN__CTL EQU CYREG_PRT2_CTL
ICHAN__DM0 EQU CYREG_PRT2_DM0
ICHAN__DM1 EQU CYREG_PRT2_DM1
ICHAN__DM2 EQU CYREG_PRT2_DM2
ICHAN__DR EQU CYREG_PRT2_DR
ICHAN__INP_DIS EQU CYREG_PRT2_INP_DIS
ICHAN__LCD_COM_SEG EQU CYREG_PRT2_LCD_COM_SEG
ICHAN__LCD_EN EQU CYREG_PRT2_LCD_EN
ICHAN__PORT EQU 2
ICHAN__PRT EQU CYREG_PRT2_PRT
ICHAN__PRTDSI__CAPS_SEL EQU CYREG_PRT2_CAPS_SEL
ICHAN__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT2_DBL_SYNC_IN
ICHAN__PRTDSI__OE_SEL0 EQU CYREG_PRT2_OE_SEL0
ICHAN__PRTDSI__OE_SEL1 EQU CYREG_PRT2_OE_SEL1
ICHAN__PRTDSI__OUT_SEL0 EQU CYREG_PRT2_OUT_SEL0
ICHAN__PRTDSI__OUT_SEL1 EQU CYREG_PRT2_OUT_SEL1
ICHAN__PRTDSI__SYNC_OUT EQU CYREG_PRT2_SYNC_OUT
ICHAN__PS EQU CYREG_PRT2_PS
ICHAN__SLW EQU CYREG_PRT2_SLW

; IQMUX
IQMUX_ctrl_reg__0__MASK EQU 0x01
IQMUX_ctrl_reg__0__POS EQU 0
IQMUX_ctrl_reg__16BIT_CONTROL_AUX_CTL_REG EQU CYREG_B0_UDB13_14_ACTL
IQMUX_ctrl_reg__16BIT_CONTROL_CONTROL_REG EQU CYREG_B0_UDB13_14_CTL
IQMUX_ctrl_reg__16BIT_CONTROL_COUNT_REG EQU CYREG_B0_UDB13_14_CTL
IQMUX_ctrl_reg__16BIT_COUNT_CONTROL_REG EQU CYREG_B0_UDB13_14_CTL
IQMUX_ctrl_reg__16BIT_COUNT_COUNT_REG EQU CYREG_B0_UDB13_14_CTL
IQMUX_ctrl_reg__16BIT_MASK_MASK_REG EQU CYREG_B0_UDB13_14_MSK
IQMUX_ctrl_reg__16BIT_MASK_PERIOD_REG EQU CYREG_B0_UDB13_14_MSK
IQMUX_ctrl_reg__16BIT_PERIOD_MASK_REG EQU CYREG_B0_UDB13_14_MSK
IQMUX_ctrl_reg__16BIT_PERIOD_PERIOD_REG EQU CYREG_B0_UDB13_14_MSK
IQMUX_ctrl_reg__1__MASK EQU 0x02
IQMUX_ctrl_reg__1__POS EQU 1
IQMUX_ctrl_reg__CONTROL_AUX_CTL_REG EQU CYREG_B0_UDB13_ACTL
IQMUX_ctrl_reg__CONTROL_REG EQU CYREG_B0_UDB13_CTL
IQMUX_ctrl_reg__CONTROL_ST_REG EQU CYREG_B0_UDB13_ST_CTL
IQMUX_ctrl_reg__COUNT_REG EQU CYREG_B0_UDB13_CTL
IQMUX_ctrl_reg__COUNT_ST_REG EQU CYREG_B0_UDB13_ST_CTL
IQMUX_ctrl_reg__MASK EQU 0x03
IQMUX_ctrl_reg__MASK_CTL_AUX_CTL_REG EQU CYREG_B0_UDB13_MSK_ACTL
IQMUX_ctrl_reg__PERIOD_REG EQU CYREG_B0_UDB13_MSK
IQMUX_ctrl_reg__PER_CTL_AUX_CTL_REG EQU CYREG_B0_UDB13_MSK_ACTL

; QCHAN
QCHAN__0__MASK EQU 0x10
QCHAN__0__PC EQU CYREG_PRT2_PC4
QCHAN__0__PORT EQU 2
QCHAN__0__SHIFT EQU 4
QCHAN__AG EQU CYREG_PRT2_AG
QCHAN__AMUX EQU CYREG_PRT2_AMUX
QCHAN__BIE EQU CYREG_PRT2_BIE
QCHAN__BIT_MASK EQU CYREG_PRT2_BIT_MASK
QCHAN__BYP EQU CYREG_PRT2_BYP
QCHAN__CTL EQU CYREG_PRT2_CTL
QCHAN__DM0 EQU CYREG_PRT2_DM0
QCHAN__DM1 EQU CYREG_PRT2_DM1
QCHAN__DM2 EQU CYREG_PRT2_DM2
QCHAN__DR EQU CYREG_PRT2_DR
QCHAN__INP_DIS EQU CYREG_PRT2_INP_DIS
QCHAN__LCD_COM_SEG EQU CYREG_PRT2_LCD_COM_SEG
QCHAN__LCD_EN EQU CYREG_PRT2_LCD_EN
QCHAN__PORT EQU 2
QCHAN__PRT EQU CYREG_PRT2_PRT
QCHAN__PRTDSI__CAPS_SEL EQU CYREG_PRT2_CAPS_SEL
QCHAN__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT2_DBL_SYNC_IN
QCHAN__PRTDSI__OE_SEL0 EQU CYREG_PRT2_OE_SEL0
QCHAN__PRTDSI__OE_SEL1 EQU CYREG_PRT2_OE_SEL1
QCHAN__PRTDSI__OUT_SEL0 EQU CYREG_PRT2_OUT_SEL0
QCHAN__PRTDSI__OUT_SEL1 EQU CYREG_PRT2_OUT_SEL1
QCHAN__PRTDSI__SYNC_OUT EQU CYREG_PRT2_SYNC_OUT
QCHAN__PS EQU CYREG_PRT2_PS
QCHAN__SLW EQU CYREG_PRT2_SLW

; ICLK
ICLK__0__MASK EQU 0x08
ICLK__0__PC EQU CYREG_PRT12_PC3
ICLK__0__PORT EQU 12
ICLK__0__SHIFT EQU 3
ICLK__AG EQU CYREG_PRT12_AG
ICLK__BIE EQU CYREG_PRT12_BIE
ICLK__BIT_MASK EQU CYREG_PRT12_BIT_MASK
ICLK__BYP EQU CYREG_PRT12_BYP
ICLK__DM0 EQU CYREG_PRT12_DM0
ICLK__DM1 EQU CYREG_PRT12_DM1
ICLK__DM2 EQU CYREG_PRT12_DM2
ICLK__DR EQU CYREG_PRT12_DR
ICLK__INP_DIS EQU CYREG_PRT12_INP_DIS
ICLK__MASK EQU 0x08
ICLK__PORT EQU 12
ICLK__PRT EQU CYREG_PRT12_PRT
ICLK__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT12_DBL_SYNC_IN
ICLK__PRTDSI__OE_SEL0 EQU CYREG_PRT12_OE_SEL0
ICLK__PRTDSI__OE_SEL1 EQU CYREG_PRT12_OE_SEL1
ICLK__PRTDSI__OUT_SEL0 EQU CYREG_PRT12_OUT_SEL0
ICLK__PRTDSI__OUT_SEL1 EQU CYREG_PRT12_OUT_SEL1
ICLK__PRTDSI__SYNC_OUT EQU CYREG_PRT12_SYNC_OUT
ICLK__PS EQU CYREG_PRT12_PS
ICLK__SHIFT EQU 3
ICLK__SIO_CFG EQU CYREG_PRT12_SIO_CFG
ICLK__SIO_DIFF EQU CYREG_PRT12_SIO_DIFF
ICLK__SIO_HYST_EN EQU CYREG_PRT12_SIO_HYST_EN
ICLK__SIO_REG_HIFREQ EQU CYREG_PRT12_SIO_REG_HIFREQ
ICLK__SLW EQU CYREG_PRT12_SLW

; IOUT
IOUT__0__MASK EQU 0x40
IOUT__0__PC EQU CYREG_PRT2_PC6
IOUT__0__PORT EQU 2
IOUT__0__SHIFT EQU 6
IOUT__AG EQU CYREG_PRT2_AG
IOUT__AMUX EQU CYREG_PRT2_AMUX
IOUT__BIE EQU CYREG_PRT2_BIE
IOUT__BIT_MASK EQU CYREG_PRT2_BIT_MASK
IOUT__BYP EQU CYREG_PRT2_BYP
IOUT__CTL EQU CYREG_PRT2_CTL
IOUT__DM0 EQU CYREG_PRT2_DM0
IOUT__DM1 EQU CYREG_PRT2_DM1
IOUT__DM2 EQU CYREG_PRT2_DM2
IOUT__DR EQU CYREG_PRT2_DR
IOUT__INP_DIS EQU CYREG_PRT2_INP_DIS
IOUT__LCD_COM_SEG EQU CYREG_PRT2_LCD_COM_SEG
IOUT__LCD_EN EQU CYREG_PRT2_LCD_EN
IOUT__PORT EQU 2
IOUT__PRT EQU CYREG_PRT2_PRT
IOUT__PRTDSI__CAPS_SEL EQU CYREG_PRT2_CAPS_SEL
IOUT__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT2_DBL_SYNC_IN
IOUT__PRTDSI__OE_SEL0 EQU CYREG_PRT2_OE_SEL0
IOUT__PRTDSI__OE_SEL1 EQU CYREG_PRT2_OE_SEL1
IOUT__PRTDSI__OUT_SEL0 EQU CYREG_PRT2_OUT_SEL0
IOUT__PRTDSI__OUT_SEL1 EQU CYREG_PRT2_OUT_SEL1
IOUT__PRTDSI__SYNC_OUT EQU CYREG_PRT2_SYNC_OUT
IOUT__PS EQU CYREG_PRT2_PS
IOUT__SLW EQU CYREG_PRT2_SLW

; QCLK
QCLK__0__MASK EQU 0x04
QCLK__0__PC EQU CYREG_PRT12_PC2
QCLK__0__PORT EQU 12
QCLK__0__SHIFT EQU 2
QCLK__AG EQU CYREG_PRT12_AG
QCLK__BIE EQU CYREG_PRT12_BIE
QCLK__BIT_MASK EQU CYREG_PRT12_BIT_MASK
QCLK__BYP EQU CYREG_PRT12_BYP
QCLK__DM0 EQU CYREG_PRT12_DM0
QCLK__DM1 EQU CYREG_PRT12_DM1
QCLK__DM2 EQU CYREG_PRT12_DM2
QCLK__DR EQU CYREG_PRT12_DR
QCLK__INP_DIS EQU CYREG_PRT12_INP_DIS
QCLK__MASK EQU 0x04
QCLK__PORT EQU 12
QCLK__PRT EQU CYREG_PRT12_PRT
QCLK__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT12_DBL_SYNC_IN
QCLK__PRTDSI__OE_SEL0 EQU CYREG_PRT12_OE_SEL0
QCLK__PRTDSI__OE_SEL1 EQU CYREG_PRT12_OE_SEL1
QCLK__PRTDSI__OUT_SEL0 EQU CYREG_PRT12_OUT_SEL0
QCLK__PRTDSI__OUT_SEL1 EQU CYREG_PRT12_OUT_SEL1
QCLK__PRTDSI__SYNC_OUT EQU CYREG_PRT12_SYNC_OUT
QCLK__PS EQU CYREG_PRT12_PS
QCLK__SHIFT EQU 2
QCLK__SIO_CFG EQU CYREG_PRT12_SIO_CFG
QCLK__SIO_DIFF EQU CYREG_PRT12_SIO_DIFF
QCLK__SIO_HYST_EN EQU CYREG_PRT12_SIO_HYST_EN
QCLK__SIO_REG_HIFREQ EQU CYREG_PRT12_SIO_REG_HIFREQ
QCLK__SLW EQU CYREG_PRT12_SLW

; QOUT
QOUT__0__MASK EQU 0x80
QOUT__0__PC EQU CYREG_PRT2_PC7
QOUT__0__PORT EQU 2
QOUT__0__SHIFT EQU 7
QOUT__AG EQU CYREG_PRT2_AG
QOUT__AMUX EQU CYREG_PRT2_AMUX
QOUT__BIE EQU CYREG_PRT2_BIE
QOUT__BIT_MASK EQU CYREG_PRT2_BIT_MASK
QOUT__BYP EQU CYREG_PRT2_BYP
QOUT__CTL EQU CYREG_PRT2_CTL
QOUT__DM0 EQU CYREG_PRT2_DM0
QOUT__DM1 EQU CYREG_PRT2_DM1
QOUT__DM2 EQU CYREG_PRT2_DM2
QOUT__DR EQU CYREG_PRT2_DR
QOUT__INP_DIS EQU CYREG_PRT2_INP_DIS
QOUT__LCD_COM_SEG EQU CYREG_PRT2_LCD_COM_SEG
QOUT__LCD_EN EQU CYREG_PRT2_LCD_EN
QOUT__PORT EQU 2
QOUT__PRT EQU CYREG_PRT2_PRT
QOUT__PRTDSI__CAPS_SEL EQU CYREG_PRT2_CAPS_SEL
QOUT__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT2_DBL_SYNC_IN
QOUT__PRTDSI__OE_SEL0 EQU CYREG_PRT2_OE_SEL0
QOUT__PRTDSI__OE_SEL1 EQU CYREG_PRT2_OE_SEL1
QOUT__PRTDSI__OUT_SEL0 EQU CYREG_PRT2_OUT_SEL0
QOUT__PRTDSI__OUT_SEL1 EQU CYREG_PRT2_OUT_SEL1
QOUT__PRTDSI__SYNC_OUT EQU CYREG_PRT2_SYNC_OUT
QOUT__PS EQU CYREG_PRT2_PS
QOUT__SLW EQU CYREG_PRT2_SLW

; DMA
DMA_CHANNELS_USED__MASK0 EQU 0x00010000
DMA__DRQ_CTL EQU CYREG_IDMUX_DRQ_CTL4
DMA__DRQ_NUMBER EQU 16
DMA__NUMBEROF_TDS EQU 0
DMA__PRIORITY EQU 2
DMA__TERMIN_EN EQU 0
DMA__TERMIN_SEL EQU 0
DMA__TERMOUT0_EN EQU 0
DMA__TERMOUT0_SEL EQU 0
DMA__TERMOUT1_EN EQU 0
DMA__TERMOUT1_SEL EQU 0

; Miscellaneous
; -- WARNING: define names containting LEOPARD or PANTHER are deprecated and will be removed in a future release
CYDEV_BOOTLOADER_IO_COMP_CUSTOM_IO EQU 0
CYDEV_DEBUGGING_DPS_SWD EQU 2
CYDEV_CONFIG_UNUSED_IO_AllowButWarn EQU 0
CYDEV_CONFIGURATION_MODE_COMPRESSED EQU 0
CYDEV_CONFIG_FASTBOOT_ENABLED EQU 1
CYDEV_CHIP_REV_LEOPARD_PRODUCTION EQU 3
CYDEV_CHIP_REVISION_3A_PRODUCTION EQU 3
CYDEV_CHIP_MEMBER_3A EQU 1
CYDEV_CHIP_FAMILY_PSOC3 EQU 1
CYDEV_CHIP_DIE_LEOPARD EQU 1
CYDEV_CHIP_DIE_EXPECT EQU CYDEV_CHIP_DIE_LEOPARD
CYDEV_BOOTLOADER_CHECKSUM_BASIC EQU 0
BCLK__BUS_CLK__HZ EQU 56000000
BCLK__BUS_CLK__KHZ EQU 56000
BCLK__BUS_CLK__MHZ EQU 56
CYDEV_APPLICATION_ID EQU 0x0000
CYDEV_APPLICATION_VERSION EQU 0x0000
CYDEV_BOOTLOADER_CHECKSUM EQU CYDEV_BOOTLOADER_CHECKSUM_BASIC
CYDEV_BOOTLOADER_CHECKSUM_CRC EQU 1
CYDEV_BOOTLOADER_FAST_VERIFY EQU 0
CYDEV_BOOTLOADER_VERSION EQU 0x0000
CYDEV_BOOTLOADER_WAIT_COMMAND EQU 1
CYDEV_BOOTLOADER_WAIT_TIME EQU 200
CYDEV_CHIP_DIE_ACTUAL EQU CYDEV_CHIP_DIE_EXPECT
CYDEV_CHIP_DIE_PANTHER EQU 2
CYDEV_CHIP_DIE_UNKNOWN EQU 0
CYDEV_CHIP_FAMILY_PSOC4 EQU 2
CYDEV_CHIP_FAMILY_PSOC5 EQU 3
CYDEV_CHIP_FAMILY_UNKNOWN EQU 0
CYDEV_CHIP_FAMILY_USED EQU CYDEV_CHIP_FAMILY_PSOC3
CYDEV_CHIP_JTAG_ID EQU 0x1E015069
CYDEV_CHIP_MEMBER_5A EQU 2
CYDEV_CHIP_MEMBER_UNKNOWN EQU 0
CYDEV_CHIP_MEMBER_USED EQU CYDEV_CHIP_MEMBER_3A
CYDEV_CHIP_REVISION_3A_ES1 EQU 0
CYDEV_CHIP_REVISION_3A_ES2 EQU 1
CYDEV_CHIP_REVISION_3A_ES3 EQU 3
CYDEV_CHIP_REVISION_5A_ES0 EQU 0
CYDEV_CHIP_REVISION_5A_ES1 EQU 1
CYDEV_CHIP_REVISION_5A_PRODUCTION EQU 1
CYDEV_CHIP_REVISION_USED EQU CYDEV_CHIP_REVISION_3A_PRODUCTION
CYDEV_CHIP_REV_EXPECT EQU CYDEV_CHIP_REV_LEOPARD_PRODUCTION
CYDEV_CHIP_REV_LEOPARD_ES1 EQU 0
CYDEV_CHIP_REV_LEOPARD_ES2 EQU 1
CYDEV_CHIP_REV_LEOPARD_ES3 EQU 3
CYDEV_CHIP_REV_PANTHER_ES0 EQU 0
CYDEV_CHIP_REV_PANTHER_ES1 EQU 1
CYDEV_CHIP_REV_PANTHER_PRODUCTION EQU 1
CYDEV_CONFIGURATION_CLEAR_SRAM EQU 1
CYDEV_CONFIGURATION_COMPRESSED EQU 1
CYDEV_CONFIGURATION_DMA EQU 0
CYDEV_CONFIGURATION_ECC EQU 0
CYDEV_CONFIGURATION_IMOENABLED EQU CYDEV_CONFIG_FASTBOOT_ENABLED
CYDEV_CONFIGURATION_MODE EQU CYDEV_CONFIGURATION_MODE_COMPRESSED
CYDEV_CONFIGURATION_MODE_DMA EQU 2
CYDEV_CONFIGURATION_MODE_UNCOMPRESSED EQU 1
CYDEV_CONFIG_FORCE_ROUTE EQU 0
CYDEV_CONFIG_UNUSED_IO EQU CYDEV_CONFIG_UNUSED_IO_AllowButWarn
CYDEV_CONFIG_UNUSED_IO_AllowWithInfo EQU 1
CYDEV_CONFIG_UNUSED_IO_Disallowed EQU 2
CYDEV_CUSTOM_ID EQU 0x00000000
CYDEV_DEBUGGING_DPS EQU CYDEV_DEBUGGING_DPS_SWD
CYDEV_DEBUGGING_DPS_Disable EQU 3
CYDEV_DEBUGGING_DPS_JTAG_4 EQU 1
CYDEV_DEBUGGING_DPS_JTAG_5 EQU 0
CYDEV_DEBUGGING_ENABLE EQU 1
CYDEV_DEBUGGING_REQXRES EQU 1
CYDEV_DEBUGGING_XRES EQU 1
CYDEV_DEBUG_ENABLE_MASK EQU 0x01
CYDEV_DEBUG_ENABLE_REGISTER EQU CYREG_MLOGIC_DEBUG
CYDEV_DMA_CHANNELS_AVAILABLE EQU 24
CYDEV_ECC_ENABLE EQU 0
CYDEV_INSTRUCT_CACHE_ENABLED EQU 0
CYDEV_PROJ_TYPE EQU 2
CYDEV_PROJ_TYPE_BOOTLOADER EQU 1
CYDEV_PROJ_TYPE_LOADABLE EQU 2
CYDEV_PROJ_TYPE_MULTIAPPBOOTLOADER EQU 3
CYDEV_PROJ_TYPE_STANDARD EQU 0
CYDEV_PROTECTION_ENABLE EQU 0
CYDEV_USB_CLK_OSC_LOCKING_ENABLED_AT_PWR_UP EQU 1
CYDEV_VDDA LIT '3.3'
CYDEV_VDDA_MV EQU 3300
CYDEV_VDDD LIT '3.3'
CYDEV_VDDD_MV EQU 3300
CYDEV_VDDIO0 LIT '3.3'
CYDEV_VDDIO0_MV EQU 3300
CYDEV_VDDIO1 LIT '3.3'
CYDEV_VDDIO1_MV EQU 3300
CYDEV_VDDIO2 LIT '3.3'
CYDEV_VDDIO2_MV EQU 3300
CYDEV_VDDIO3 LIT '3.3'
CYDEV_VDDIO3_MV EQU 3300
CYDEV_VIO0 LIT '3.3'
CYDEV_VIO0_MV EQU 3300
CYDEV_VIO1 LIT '3.3'
CYDEV_VIO1_MV EQU 3300
CYDEV_VIO2 LIT '3.3'
CYDEV_VIO2_MV EQU 3300
CYDEV_VIO3 LIT '3.3'
CYDEV_VIO3_MV EQU 3300
CyBtldr_Custom_Interface EQU CYDEV_BOOTLOADER_IO_COMP_CUSTOM_IO
CYDEV_BOOTLOADER_ENABLE EQU 0

#endif /* INCLUDED_CYFITTERKEIL_INC */
