#ifndef INCLUDED_CYFITTER_H
#define INCLUDED_CYFITTER_H
#include <cydevice.h>
#include <cydevice_trm.h>

/* USBUART_bus_reset */
#define USBUART_bus_reset__ES2_PATCH 0
#define USBUART_bus_reset__INTC_CLR_EN_REG CYREG_INTC_CLR_EN2
#define USBUART_bus_reset__INTC_CLR_PD_REG CYREG_INTC_CLR_PD2
#define USBUART_bus_reset__INTC_MASK 0x80u
#define USBUART_bus_reset__INTC_NUMBER 23
#define USBUART_bus_reset__INTC_PRIOR_NUM 7
#define USBUART_bus_reset__INTC_PRIOR_REG CYREG_INTC_PRIOR23
#define USBUART_bus_reset__INTC_SET_EN_REG CYREG_INTC_SET_EN2
#define USBUART_bus_reset__INTC_SET_PD_REG CYREG_INTC_SET_PD2
#define USBUART_bus_reset__INTC_VECT (CYREG_INTC_VECT_MBASE+0x2Eu)

/* USBUART_arb_int */
#define USBUART_arb_int__ES2_PATCH 0
#define USBUART_arb_int__INTC_CLR_EN_REG CYREG_INTC_CLR_EN2
#define USBUART_arb_int__INTC_CLR_PD_REG CYREG_INTC_CLR_PD2
#define USBUART_arb_int__INTC_MASK 0x40u
#define USBUART_arb_int__INTC_NUMBER 22
#define USBUART_arb_int__INTC_PRIOR_NUM 7
#define USBUART_arb_int__INTC_PRIOR_REG CYREG_INTC_PRIOR22
#define USBUART_arb_int__INTC_SET_EN_REG CYREG_INTC_SET_EN2
#define USBUART_arb_int__INTC_SET_PD_REG CYREG_INTC_SET_PD2
#define USBUART_arb_int__INTC_VECT (CYREG_INTC_VECT_MBASE+0x2Cu)

/* USBUART_ord_int */
#define USBUART_ord_int__ES2_PATCH 0
#define USBUART_ord_int__INTC_CLR_EN_REG CYREG_INTC_CLR_EN3
#define USBUART_ord_int__INTC_CLR_PD_REG CYREG_INTC_CLR_PD3
#define USBUART_ord_int__INTC_MASK 0x02u
#define USBUART_ord_int__INTC_NUMBER 25
#define USBUART_ord_int__INTC_PRIOR_NUM 7
#define USBUART_ord_int__INTC_PRIOR_REG CYREG_INTC_PRIOR25
#define USBUART_ord_int__INTC_SET_EN_REG CYREG_INTC_SET_EN3
#define USBUART_ord_int__INTC_SET_PD_REG CYREG_INTC_SET_PD3
#define USBUART_ord_int__INTC_VECT (CYREG_INTC_VECT_MBASE+0x32)

/* USBUART_sof_int */
#define USBUART_sof_int__ES2_PATCH 0
#define USBUART_sof_int__INTC_CLR_EN_REG CYREG_INTC_CLR_EN2
#define USBUART_sof_int__INTC_CLR_PD_REG CYREG_INTC_CLR_PD2
#define USBUART_sof_int__INTC_MASK 0x20u
#define USBUART_sof_int__INTC_NUMBER 21
#define USBUART_sof_int__INTC_PRIOR_NUM 7
#define USBUART_sof_int__INTC_PRIOR_REG CYREG_INTC_PRIOR21
#define USBUART_sof_int__INTC_SET_EN_REG CYREG_INTC_SET_EN2
#define USBUART_sof_int__INTC_SET_PD_REG CYREG_INTC_SET_PD2
#define USBUART_sof_int__INTC_VECT (CYREG_INTC_VECT_MBASE+0x2Au)

/* ADC_Bypass_P03 */
#define ADC_Bypass_P03__0__MASK 0x08u
#define ADC_Bypass_P03__0__PC CYREG_PRT0_PC3
#define ADC_Bypass_P03__0__PORT 0
#define ADC_Bypass_P03__0__SHIFT 3
#define ADC_Bypass_P03__AG CYREG_PRT0_AG
#define ADC_Bypass_P03__AMUX CYREG_PRT0_AMUX
#define ADC_Bypass_P03__BIE CYREG_PRT0_BIE
#define ADC_Bypass_P03__BIT_MASK CYREG_PRT0_BIT_MASK
#define ADC_Bypass_P03__BYP CYREG_PRT0_BYP
#define ADC_Bypass_P03__CTL CYREG_PRT0_CTL
#define ADC_Bypass_P03__DM0 CYREG_PRT0_DM0
#define ADC_Bypass_P03__DM1 CYREG_PRT0_DM1
#define ADC_Bypass_P03__DM2 CYREG_PRT0_DM2
#define ADC_Bypass_P03__DR CYREG_PRT0_DR
#define ADC_Bypass_P03__INP_DIS CYREG_PRT0_INP_DIS
#define ADC_Bypass_P03__LCD_COM_SEG CYREG_PRT0_LCD_COM_SEG
#define ADC_Bypass_P03__LCD_EN CYREG_PRT0_LCD_EN
#define ADC_Bypass_P03__PORT 0
#define ADC_Bypass_P03__PRT CYREG_PRT0_PRT
#define ADC_Bypass_P03__PRTDSI__CAPS_SEL CYREG_PRT0_CAPS_SEL
#define ADC_Bypass_P03__PRTDSI__DBL_SYNC_IN CYREG_PRT0_DBL_SYNC_IN
#define ADC_Bypass_P03__PRTDSI__OE_SEL0 CYREG_PRT0_OE_SEL0
#define ADC_Bypass_P03__PRTDSI__OE_SEL1 CYREG_PRT0_OE_SEL1
#define ADC_Bypass_P03__PRTDSI__OUT_SEL0 CYREG_PRT0_OUT_SEL0
#define ADC_Bypass_P03__PRTDSI__OUT_SEL1 CYREG_PRT0_OUT_SEL1
#define ADC_Bypass_P03__PRTDSI__SYNC_OUT CYREG_PRT0_SYNC_OUT
#define ADC_Bypass_P03__PS CYREG_PRT0_PS
#define ADC_Bypass_P03__SLW CYREG_PRT0_SLW

/* ADC_Ext_CP_Clk */
#define ADC_Ext_CP_Clk__CFG0 CYREG_CLKDIST_DCFG1_CFG0
#define ADC_Ext_CP_Clk__CFG1 CYREG_CLKDIST_DCFG1_CFG1
#define ADC_Ext_CP_Clk__CFG2 CYREG_CLKDIST_DCFG1_CFG2
#define ADC_Ext_CP_Clk__CFG2_SRC_SEL_MASK 0x07u
#define ADC_Ext_CP_Clk__PM_ACT_CFG CYREG_PM_ACT_CFG2
#define ADC_Ext_CP_Clk__PM_ACT_MSK 0x02u
#define ADC_Ext_CP_Clk__PM_STBY_CFG CYREG_PM_STBY_CFG2
#define ADC_Ext_CP_Clk__PM_STBY_MSK 0x02u

/* IQ_Generator */
#define IQ_Generator_IQDividerMax__0__MASK 0x01u
#define IQ_Generator_IQDividerMax__0__POS 0
#define IQ_Generator_IQDividerMax__16BIT_CONTROL_AUX_CTL_REG CYREG_B1_UDB06_07_ACTL
#define IQ_Generator_IQDividerMax__16BIT_CONTROL_CONTROL_REG CYREG_B1_UDB06_07_CTL
#define IQ_Generator_IQDividerMax__16BIT_CONTROL_COUNT_REG CYREG_B1_UDB06_07_CTL
#define IQ_Generator_IQDividerMax__16BIT_COUNT_CONTROL_REG CYREG_B1_UDB06_07_CTL
#define IQ_Generator_IQDividerMax__16BIT_COUNT_COUNT_REG CYREG_B1_UDB06_07_CTL
#define IQ_Generator_IQDividerMax__16BIT_MASK_MASK_REG CYREG_B1_UDB06_07_MSK
#define IQ_Generator_IQDividerMax__16BIT_MASK_PERIOD_REG CYREG_B1_UDB06_07_MSK
#define IQ_Generator_IQDividerMax__16BIT_PERIOD_MASK_REG CYREG_B1_UDB06_07_MSK
#define IQ_Generator_IQDividerMax__16BIT_PERIOD_PERIOD_REG CYREG_B1_UDB06_07_MSK
#define IQ_Generator_IQDividerMax__1__MASK 0x02u
#define IQ_Generator_IQDividerMax__1__POS 1
#define IQ_Generator_IQDividerMax__2__MASK 0x04u
#define IQ_Generator_IQDividerMax__2__POS 2
#define IQ_Generator_IQDividerMax__3__MASK 0x08u
#define IQ_Generator_IQDividerMax__3__POS 3
#define IQ_Generator_IQDividerMax__CONTROL_AUX_CTL_REG CYREG_B1_UDB06_ACTL
#define IQ_Generator_IQDividerMax__CONTROL_REG CYREG_B1_UDB06_CTL
#define IQ_Generator_IQDividerMax__CONTROL_ST_REG CYREG_B1_UDB06_ST_CTL
#define IQ_Generator_IQDividerMax__COUNT_REG CYREG_B1_UDB06_CTL
#define IQ_Generator_IQDividerMax__COUNT_ST_REG CYREG_B1_UDB06_ST_CTL
#define IQ_Generator_IQDividerMax__MASK 0x0Fu
#define IQ_Generator_IQDividerMax__MASK_CTL_AUX_CTL_REG CYREG_B1_UDB06_MSK_ACTL
#define IQ_Generator_IQDividerMax__PERIOD_REG CYREG_B1_UDB06_MSK
#define IQ_Generator_IQDividerMax__PER_CTL_AUX_CTL_REG CYREG_B1_UDB06_MSK_ACTL

/* USBUART_ep_0 */
#define USBUART_ep_0__ES2_PATCH 0
#define USBUART_ep_0__INTC_CLR_EN_REG CYREG_INTC_CLR_EN3
#define USBUART_ep_0__INTC_CLR_PD_REG CYREG_INTC_CLR_PD3
#define USBUART_ep_0__INTC_MASK 0x01u
#define USBUART_ep_0__INTC_NUMBER 24
#define USBUART_ep_0__INTC_PRIOR_NUM 7
#define USBUART_ep_0__INTC_PRIOR_REG CYREG_INTC_PRIOR24
#define USBUART_ep_0__INTC_SET_EN_REG CYREG_INTC_SET_EN3
#define USBUART_ep_0__INTC_SET_PD_REG CYREG_INTC_SET_PD3
#define USBUART_ep_0__INTC_VECT (CYREG_INTC_VECT_MBASE+0x30)

/* USBUART_ep_1 */
#define USBUART_ep_1__ES2_PATCH 0
#define USBUART_ep_1__INTC_CLR_EN_REG CYREG_INTC_CLR_EN0
#define USBUART_ep_1__INTC_CLR_PD_REG CYREG_INTC_CLR_PD0
#define USBUART_ep_1__INTC_MASK 0x02u
#define USBUART_ep_1__INTC_NUMBER 1
#define USBUART_ep_1__INTC_PRIOR_NUM 7
#define USBUART_ep_1__INTC_PRIOR_REG CYREG_INTC_PRIOR1
#define USBUART_ep_1__INTC_SET_EN_REG CYREG_INTC_SET_EN0
#define USBUART_ep_1__INTC_SET_PD_REG CYREG_INTC_SET_PD0
#define USBUART_ep_1__INTC_VECT (CYREG_INTC_VECT_MBASE+0x02)

/* USBUART_ep_2 */
#define USBUART_ep_2__ES2_PATCH 0
#define USBUART_ep_2__INTC_CLR_EN_REG CYREG_INTC_CLR_EN0
#define USBUART_ep_2__INTC_CLR_PD_REG CYREG_INTC_CLR_PD0
#define USBUART_ep_2__INTC_MASK 0x04u
#define USBUART_ep_2__INTC_NUMBER 2
#define USBUART_ep_2__INTC_PRIOR_NUM 7
#define USBUART_ep_2__INTC_PRIOR_REG CYREG_INTC_PRIOR2
#define USBUART_ep_2__INTC_SET_EN_REG CYREG_INTC_SET_EN0
#define USBUART_ep_2__INTC_SET_PD_REG CYREG_INTC_SET_PD0
#define USBUART_ep_2__INTC_VECT (CYREG_INTC_VECT_MBASE+0x04)

/* USBUART_ep_3 */
#define USBUART_ep_3__ES2_PATCH 0
#define USBUART_ep_3__INTC_CLR_EN_REG CYREG_INTC_CLR_EN2
#define USBUART_ep_3__INTC_CLR_PD_REG CYREG_INTC_CLR_PD2
#define USBUART_ep_3__INTC_MASK 0x10u
#define USBUART_ep_3__INTC_NUMBER 20
#define USBUART_ep_3__INTC_PRIOR_NUM 7
#define USBUART_ep_3__INTC_PRIOR_REG CYREG_INTC_PRIOR20
#define USBUART_ep_3__INTC_SET_EN_REG CYREG_INTC_SET_EN2
#define USBUART_ep_3__INTC_SET_PD_REG CYREG_INTC_SET_PD2
#define USBUART_ep_3__INTC_VECT (CYREG_INTC_VECT_MBASE+0x28)

/* USBUART_ep_4 */
#define USBUART_ep_4__ES2_PATCH 0
#define USBUART_ep_4__INTC_CLR_EN_REG CYREG_INTC_CLR_EN1
#define USBUART_ep_4__INTC_CLR_PD_REG CYREG_INTC_CLR_PD1
#define USBUART_ep_4__INTC_MASK 0x80u
#define USBUART_ep_4__INTC_NUMBER 15
#define USBUART_ep_4__INTC_PRIOR_NUM 7
#define USBUART_ep_4__INTC_PRIOR_REG CYREG_INTC_PRIOR15
#define USBUART_ep_4__INTC_SET_EN_REG CYREG_INTC_SET_EN1
#define USBUART_ep_4__INTC_SET_PD_REG CYREG_INTC_SET_PD1
#define USBUART_ep_4__INTC_VECT (CYREG_INTC_VECT_MBASE+0x1Eu)

/* USBUART_ep_5 */
#define USBUART_ep_5__ES2_PATCH 0
#define USBUART_ep_5__INTC_CLR_EN_REG CYREG_INTC_CLR_EN1
#define USBUART_ep_5__INTC_CLR_PD_REG CYREG_INTC_CLR_PD1
#define USBUART_ep_5__INTC_MASK 0x20u
#define USBUART_ep_5__INTC_NUMBER 13
#define USBUART_ep_5__INTC_PRIOR_NUM 7
#define USBUART_ep_5__INTC_PRIOR_REG CYREG_INTC_PRIOR13
#define USBUART_ep_5__INTC_SET_EN_REG CYREG_INTC_SET_EN1
#define USBUART_ep_5__INTC_SET_PD_REG CYREG_INTC_SET_PD1
#define USBUART_ep_5__INTC_VECT (CYREG_INTC_VECT_MBASE+0x1Au)

/* USBUART_ep_6 */
#define USBUART_ep_6__ES2_PATCH 0
#define USBUART_ep_6__INTC_CLR_EN_REG CYREG_INTC_CLR_EN1
#define USBUART_ep_6__INTC_CLR_PD_REG CYREG_INTC_CLR_PD1
#define USBUART_ep_6__INTC_MASK 0x10u
#define USBUART_ep_6__INTC_NUMBER 12
#define USBUART_ep_6__INTC_PRIOR_NUM 7
#define USBUART_ep_6__INTC_PRIOR_REG CYREG_INTC_PRIOR12
#define USBUART_ep_6__INTC_SET_EN_REG CYREG_INTC_SET_EN1
#define USBUART_ep_6__INTC_SET_PD_REG CYREG_INTC_SET_PD1
#define USBUART_ep_6__INTC_VECT (CYREG_INTC_VECT_MBASE+0x18)

/* USBUART_ep_7 */
#define USBUART_ep_7__ES2_PATCH 0
#define USBUART_ep_7__INTC_CLR_EN_REG CYREG_INTC_CLR_EN0
#define USBUART_ep_7__INTC_CLR_PD_REG CYREG_INTC_CLR_PD0
#define USBUART_ep_7__INTC_MASK 0x01u
#define USBUART_ep_7__INTC_NUMBER 0
#define USBUART_ep_7__INTC_PRIOR_NUM 7
#define USBUART_ep_7__INTC_PRIOR_REG CYREG_INTC_PRIOR0
#define USBUART_ep_7__INTC_SET_EN_REG CYREG_INTC_SET_EN0
#define USBUART_ep_7__INTC_SET_PD_REG CYREG_INTC_SET_PD0
#define USBUART_ep_7__INTC_VECT (CYREG_INTC_VECT_MBASE+0x00)

/* USBUART_ep_8 */
#define USBUART_ep_8__ES2_PATCH 0
#define USBUART_ep_8__INTC_CLR_EN_REG CYREG_INTC_CLR_EN2
#define USBUART_ep_8__INTC_CLR_PD_REG CYREG_INTC_CLR_PD2
#define USBUART_ep_8__INTC_MASK 0x01u
#define USBUART_ep_8__INTC_NUMBER 16
#define USBUART_ep_8__INTC_PRIOR_NUM 7
#define USBUART_ep_8__INTC_PRIOR_REG CYREG_INTC_PRIOR16
#define USBUART_ep_8__INTC_SET_EN_REG CYREG_INTC_SET_EN2
#define USBUART_ep_8__INTC_SET_PD_REG CYREG_INTC_SET_PD2
#define USBUART_ep_8__INTC_VECT (CYREG_INTC_VECT_MBASE+0x20)

/* ADC_theACLK */
#define ADC_theACLK__CFG0 CYREG_CLKDIST_ACFG0_CFG0
#define ADC_theACLK__CFG1 CYREG_CLKDIST_ACFG0_CFG1
#define ADC_theACLK__CFG2 CYREG_CLKDIST_ACFG0_CFG2
#define ADC_theACLK__CFG2_SRC_SEL_MASK 0x07u
#define ADC_theACLK__CFG3 CYREG_CLKDIST_ACFG0_CFG3
#define ADC_theACLK__CFG3_PHASE_DLY_MASK 0x0Fu
#define ADC_theACLK__PM_ACT_CFG CYREG_PM_ACT_CFG1
#define ADC_theACLK__PM_ACT_MSK 0x01u
#define ADC_theACLK__PM_STBY_CFG CYREG_PM_STBY_CFG1
#define ADC_theACLK__PM_STBY_MSK 0x01u

/* Clock_FracN */
#define Clock_FracN__CFG0 CYREG_CLKDIST_DCFG0_CFG0
#define Clock_FracN__CFG1 CYREG_CLKDIST_DCFG0_CFG1
#define Clock_FracN__CFG2 CYREG_CLKDIST_DCFG0_CFG2
#define Clock_FracN__CFG2_SRC_SEL_MASK 0x07u
#define Clock_FracN__PM_ACT_CFG CYREG_PM_ACT_CFG2
#define Clock_FracN__PM_ACT_MSK 0x01u
#define Clock_FracN__PM_STBY_CFG CYREG_PM_STBY_CFG2
#define Clock_FracN__PM_STBY_MSK 0x01u

/* USBUART_USB */
#define USBUART_USB__ARB_CFG CYREG_USB_ARB_CFG
#define USBUART_USB__ARB_EP1_CFG CYREG_USB_ARB_EP1_CFG
#define USBUART_USB__ARB_EP1_INT_EN CYREG_USB_ARB_EP1_INT_EN
#define USBUART_USB__ARB_EP1_SR CYREG_USB_ARB_EP1_SR
#define USBUART_USB__ARB_EP2_CFG CYREG_USB_ARB_EP2_CFG
#define USBUART_USB__ARB_EP2_INT_EN CYREG_USB_ARB_EP2_INT_EN
#define USBUART_USB__ARB_EP2_SR CYREG_USB_ARB_EP2_SR
#define USBUART_USB__ARB_EP3_CFG CYREG_USB_ARB_EP3_CFG
#define USBUART_USB__ARB_EP3_INT_EN CYREG_USB_ARB_EP3_INT_EN
#define USBUART_USB__ARB_EP3_SR CYREG_USB_ARB_EP3_SR
#define USBUART_USB__ARB_EP4_CFG CYREG_USB_ARB_EP4_CFG
#define USBUART_USB__ARB_EP4_INT_EN CYREG_USB_ARB_EP4_INT_EN
#define USBUART_USB__ARB_EP4_SR CYREG_USB_ARB_EP4_SR
#define USBUART_USB__ARB_EP5_CFG CYREG_USB_ARB_EP5_CFG
#define USBUART_USB__ARB_EP5_INT_EN CYREG_USB_ARB_EP5_INT_EN
#define USBUART_USB__ARB_EP5_SR CYREG_USB_ARB_EP5_SR
#define USBUART_USB__ARB_EP6_CFG CYREG_USB_ARB_EP6_CFG
#define USBUART_USB__ARB_EP6_INT_EN CYREG_USB_ARB_EP6_INT_EN
#define USBUART_USB__ARB_EP6_SR CYREG_USB_ARB_EP6_SR
#define USBUART_USB__ARB_EP7_CFG CYREG_USB_ARB_EP7_CFG
#define USBUART_USB__ARB_EP7_INT_EN CYREG_USB_ARB_EP7_INT_EN
#define USBUART_USB__ARB_EP7_SR CYREG_USB_ARB_EP7_SR
#define USBUART_USB__ARB_EP8_CFG CYREG_USB_ARB_EP8_CFG
#define USBUART_USB__ARB_EP8_INT_EN CYREG_USB_ARB_EP8_INT_EN
#define USBUART_USB__ARB_EP8_SR CYREG_USB_ARB_EP8_SR
#define USBUART_USB__ARB_INT_EN CYREG_USB_ARB_INT_EN
#define USBUART_USB__ARB_INT_SR CYREG_USB_ARB_INT_SR
#define USBUART_USB__ARB_RW1_DR CYREG_USB_ARB_RW1_DR
#define USBUART_USB__ARB_RW1_RA CYREG_USB_ARB_RW1_RA
#define USBUART_USB__ARB_RW1_RA_MSB CYREG_USB_ARB_RW1_RA_MSB
#define USBUART_USB__ARB_RW1_WA CYREG_USB_ARB_RW1_WA
#define USBUART_USB__ARB_RW1_WA_MSB CYREG_USB_ARB_RW1_WA_MSB
#define USBUART_USB__ARB_RW2_DR CYREG_USB_ARB_RW2_DR
#define USBUART_USB__ARB_RW2_RA CYREG_USB_ARB_RW2_RA
#define USBUART_USB__ARB_RW2_RA_MSB CYREG_USB_ARB_RW2_RA_MSB
#define USBUART_USB__ARB_RW2_WA CYREG_USB_ARB_RW2_WA
#define USBUART_USB__ARB_RW2_WA_MSB CYREG_USB_ARB_RW2_WA_MSB
#define USBUART_USB__ARB_RW3_DR CYREG_USB_ARB_RW3_DR
#define USBUART_USB__ARB_RW3_RA CYREG_USB_ARB_RW3_RA
#define USBUART_USB__ARB_RW3_RA_MSB CYREG_USB_ARB_RW3_RA_MSB
#define USBUART_USB__ARB_RW3_WA CYREG_USB_ARB_RW3_WA
#define USBUART_USB__ARB_RW3_WA_MSB CYREG_USB_ARB_RW3_WA_MSB
#define USBUART_USB__ARB_RW4_DR CYREG_USB_ARB_RW4_DR
#define USBUART_USB__ARB_RW4_RA CYREG_USB_ARB_RW4_RA
#define USBUART_USB__ARB_RW4_RA_MSB CYREG_USB_ARB_RW4_RA_MSB
#define USBUART_USB__ARB_RW4_WA CYREG_USB_ARB_RW4_WA
#define USBUART_USB__ARB_RW4_WA_MSB CYREG_USB_ARB_RW4_WA_MSB
#define USBUART_USB__ARB_RW5_DR CYREG_USB_ARB_RW5_DR
#define USBUART_USB__ARB_RW5_RA CYREG_USB_ARB_RW5_RA
#define USBUART_USB__ARB_RW5_RA_MSB CYREG_USB_ARB_RW5_RA_MSB
#define USBUART_USB__ARB_RW5_WA CYREG_USB_ARB_RW5_WA
#define USBUART_USB__ARB_RW5_WA_MSB CYREG_USB_ARB_RW5_WA_MSB
#define USBUART_USB__ARB_RW6_DR CYREG_USB_ARB_RW6_DR
#define USBUART_USB__ARB_RW6_RA CYREG_USB_ARB_RW6_RA
#define USBUART_USB__ARB_RW6_RA_MSB CYREG_USB_ARB_RW6_RA_MSB
#define USBUART_USB__ARB_RW6_WA CYREG_USB_ARB_RW6_WA
#define USBUART_USB__ARB_RW6_WA_MSB CYREG_USB_ARB_RW6_WA_MSB
#define USBUART_USB__ARB_RW7_DR CYREG_USB_ARB_RW7_DR
#define USBUART_USB__ARB_RW7_RA CYREG_USB_ARB_RW7_RA
#define USBUART_USB__ARB_RW7_RA_MSB CYREG_USB_ARB_RW7_RA_MSB
#define USBUART_USB__ARB_RW7_WA CYREG_USB_ARB_RW7_WA
#define USBUART_USB__ARB_RW7_WA_MSB CYREG_USB_ARB_RW7_WA_MSB
#define USBUART_USB__ARB_RW8_DR CYREG_USB_ARB_RW8_DR
#define USBUART_USB__ARB_RW8_RA CYREG_USB_ARB_RW8_RA
#define USBUART_USB__ARB_RW8_RA_MSB CYREG_USB_ARB_RW8_RA_MSB
#define USBUART_USB__ARB_RW8_WA CYREG_USB_ARB_RW8_WA
#define USBUART_USB__ARB_RW8_WA_MSB CYREG_USB_ARB_RW8_WA_MSB
#define USBUART_USB__BUF_SIZE CYREG_USB_BUF_SIZE
#define USBUART_USB__BUS_RST_CNT CYREG_USB_BUS_RST_CNT
#define USBUART_USB__CR0 CYREG_USB_CR0
#define USBUART_USB__CR1 CYREG_USB_CR1
#define USBUART_USB__CWA CYREG_USB_CWA
#define USBUART_USB__CWA_MSB CYREG_USB_CWA_MSB
#define USBUART_USB__DMA_THRES CYREG_USB_DMA_THRES
#define USBUART_USB__DMA_THRES_MSB CYREG_USB_DMA_THRES_MSB
#define USBUART_USB__DYN_RECONFIG CYREG_USB_DYN_RECONFIG
#define USBUART_USB__EP0_CNT CYREG_USB_EP0_CNT
#define USBUART_USB__EP0_CR CYREG_USB_EP0_CR
#define USBUART_USB__EP0_DR0 CYREG_USB_EP0_DR0
#define USBUART_USB__EP0_DR1 CYREG_USB_EP0_DR1
#define USBUART_USB__EP0_DR2 CYREG_USB_EP0_DR2
#define USBUART_USB__EP0_DR3 CYREG_USB_EP0_DR3
#define USBUART_USB__EP0_DR4 CYREG_USB_EP0_DR4
#define USBUART_USB__EP0_DR5 CYREG_USB_EP0_DR5
#define USBUART_USB__EP0_DR6 CYREG_USB_EP0_DR6
#define USBUART_USB__EP0_DR7 CYREG_USB_EP0_DR7
#define USBUART_USB__EP_ACTIVE CYREG_USB_EP_ACTIVE
#define USBUART_USB__EP_TYPE CYREG_USB_EP_TYPE
#define USBUART_USB__MEM_DATA CYREG_USB_MEM_DATA_MBASE
#define USBUART_USB__OSCLK_DR0 CYREG_USB_OSCLK_DR0
#define USBUART_USB__OSCLK_DR1 CYREG_USB_OSCLK_DR1
#define USBUART_USB__PM_ACT_CFG CYREG_PM_ACT_CFG5
#define USBUART_USB__PM_ACT_MSK 0x01u
#define USBUART_USB__PM_STBY_CFG CYREG_PM_STBY_CFG5
#define USBUART_USB__PM_STBY_MSK 0x01u
#define USBUART_USB__SIE_EP1_CNT0 CYREG_USB_SIE_EP1_CNT0
#define USBUART_USB__SIE_EP1_CNT1 CYREG_USB_SIE_EP1_CNT1
#define USBUART_USB__SIE_EP1_CR0 CYREG_USB_SIE_EP1_CR0
#define USBUART_USB__SIE_EP2_CNT0 CYREG_USB_SIE_EP2_CNT0
#define USBUART_USB__SIE_EP2_CNT1 CYREG_USB_SIE_EP2_CNT1
#define USBUART_USB__SIE_EP2_CR0 CYREG_USB_SIE_EP2_CR0
#define USBUART_USB__SIE_EP3_CNT0 CYREG_USB_SIE_EP3_CNT0
#define USBUART_USB__SIE_EP3_CNT1 CYREG_USB_SIE_EP3_CNT1
#define USBUART_USB__SIE_EP3_CR0 CYREG_USB_SIE_EP3_CR0
#define USBUART_USB__SIE_EP4_CNT0 CYREG_USB_SIE_EP4_CNT0
#define USBUART_USB__SIE_EP4_CNT1 CYREG_USB_SIE_EP4_CNT1
#define USBUART_USB__SIE_EP4_CR0 CYREG_USB_SIE_EP4_CR0
#define USBUART_USB__SIE_EP5_CNT0 CYREG_USB_SIE_EP5_CNT0
#define USBUART_USB__SIE_EP5_CNT1 CYREG_USB_SIE_EP5_CNT1
#define USBUART_USB__SIE_EP5_CR0 CYREG_USB_SIE_EP5_CR0
#define USBUART_USB__SIE_EP6_CNT0 CYREG_USB_SIE_EP6_CNT0
#define USBUART_USB__SIE_EP6_CNT1 CYREG_USB_SIE_EP6_CNT1
#define USBUART_USB__SIE_EP6_CR0 CYREG_USB_SIE_EP6_CR0
#define USBUART_USB__SIE_EP7_CNT0 CYREG_USB_SIE_EP7_CNT0
#define USBUART_USB__SIE_EP7_CNT1 CYREG_USB_SIE_EP7_CNT1
#define USBUART_USB__SIE_EP7_CR0 CYREG_USB_SIE_EP7_CR0
#define USBUART_USB__SIE_EP8_CNT0 CYREG_USB_SIE_EP8_CNT0
#define USBUART_USB__SIE_EP8_CNT1 CYREG_USB_SIE_EP8_CNT1
#define USBUART_USB__SIE_EP8_CR0 CYREG_USB_SIE_EP8_CR0
#define USBUART_USB__SIE_EP_INT_EN CYREG_USB_SIE_EP_INT_EN
#define USBUART_USB__SIE_EP_INT_SR CYREG_USB_SIE_EP_INT_SR
#define USBUART_USB__SOF0 CYREG_USB_SOF0
#define USBUART_USB__SOF1 CYREG_USB_SOF1
#define USBUART_USB__USBIO_CR0 CYREG_USB_USBIO_CR0
#define USBUART_USB__USBIO_CR1 CYREG_USB_USBIO_CR1
#define USBUART_USB__USBIO_CR2 CYREG_USB_USBIO_CR2
#define USBUART_USB__USB_CLK_EN CYREG_USB_USB_CLK_EN

/* VDAC_viDAC8 */
#define VDAC_viDAC8__CR0 CYREG_DAC2_CR0
#define VDAC_viDAC8__CR1 CYREG_DAC2_CR1
#define VDAC_viDAC8__D CYREG_DAC2_D
#define VDAC_viDAC8__PM_ACT_CFG CYREG_PM_ACT_CFG8
#define VDAC_viDAC8__PM_ACT_MSK 0x04u
#define VDAC_viDAC8__PM_STBY_CFG CYREG_PM_STBY_CFG8
#define VDAC_viDAC8__PM_STBY_MSK 0x04u
#define VDAC_viDAC8__STROBE CYREG_DAC2_STROBE
#define VDAC_viDAC8__SW0 CYREG_DAC2_SW0
#define VDAC_viDAC8__SW2 CYREG_DAC2_SW2
#define VDAC_viDAC8__SW3 CYREG_DAC2_SW3
#define VDAC_viDAC8__SW4 CYREG_DAC2_SW4
#define VDAC_viDAC8__TR CYREG_DAC2_TR
#define VDAC_viDAC8__TRIM__M1 CYREG_FLSHID_CUST_TABLES_DAC2_M1
#define VDAC_viDAC8__TRIM__M2 CYREG_FLSHID_CUST_TABLES_DAC2_M2
#define VDAC_viDAC8__TRIM__M3 CYREG_FLSHID_CUST_TABLES_DAC2_M3
#define VDAC_viDAC8__TRIM__M4 CYREG_FLSHID_CUST_TABLES_DAC2_M4
#define VDAC_viDAC8__TRIM__M5 CYREG_FLSHID_CUST_TABLES_DAC2_M5
#define VDAC_viDAC8__TRIM__M6 CYREG_FLSHID_CUST_TABLES_DAC2_M6
#define VDAC_viDAC8__TRIM__M7 CYREG_FLSHID_CUST_TABLES_DAC2_M7
#define VDAC_viDAC8__TRIM__M8 CYREG_FLSHID_CUST_TABLES_DAC2_M8
#define VDAC_viDAC8__TST CYREG_DAC2_TST

/* Filter_DFB */
#define Filter_DFB__ACU_SRAM_DATA CYREG_DFB0_ACU_SRAM_DATA_MBASE
#define Filter_DFB__COHER CYREG_DFB0_COHER
#define Filter_DFB__CR CYREG_DFB0_CR
#define Filter_DFB__CSA_SRAM_DATA CYREG_DFB0_CSA_SRAM_DATA_MBASE
#define Filter_DFB__CSB_SRAM_DATA CYREG_DFB0_CSB_SRAM_DATA_MBASE
#define Filter_DFB__DALIGN CYREG_DFB0_DALIGN
#define Filter_DFB__DMA_CTRL CYREG_DFB0_DMA_CTRL
#define Filter_DFB__DPA_SRAM_DATA CYREG_DFB0_DPA_SRAM_DATA_MBASE
#define Filter_DFB__DPB_SRAM_DATA CYREG_DFB0_DPB_SRAM_DATA_MBASE
#define Filter_DFB__DSI_CTRL CYREG_DFB0_DSI_CTRL
#define Filter_DFB__FSM_SRAM_DATA CYREG_DFB0_FSM_SRAM_DATA_MBASE
#define Filter_DFB__HOLDA CYREG_DFB0_HOLDA
#define Filter_DFB__HOLDAH CYREG_DFB0_HOLDAH
#define Filter_DFB__HOLDAM CYREG_DFB0_HOLDAM
#define Filter_DFB__HOLDAS CYREG_DFB0_HOLDAS
#define Filter_DFB__HOLDB CYREG_DFB0_HOLDB
#define Filter_DFB__HOLDBH CYREG_DFB0_HOLDBH
#define Filter_DFB__HOLDBM CYREG_DFB0_HOLDBM
#define Filter_DFB__HOLDBS CYREG_DFB0_HOLDBS
#define Filter_DFB__INT_CTRL CYREG_DFB0_INT_CTRL
#define Filter_DFB__PM_ACT_CFG CYREG_PM_ACT_CFG6
#define Filter_DFB__PM_ACT_MSK 0x10u
#define Filter_DFB__PM_STBY_CFG CYREG_PM_STBY_CFG6
#define Filter_DFB__PM_STBY_MSK 0x10u
#define Filter_DFB__RAM_DIR CYREG_DFB0_RAM_DIR
#define Filter_DFB__RAM_EN CYREG_DFB0_RAM_EN
#define Filter_DFB__SEMA CYREG_DFB0_SEMA
#define Filter_DFB__SR CYREG_DFB0_SR
#define Filter_DFB__STAGEA CYREG_DFB0_STAGEA
#define Filter_DFB__STAGEAH CYREG_DFB0_STAGEAH
#define Filter_DFB__STAGEAM CYREG_DFB0_STAGEAM
#define Filter_DFB__STAGEB CYREG_DFB0_STAGEB
#define Filter_DFB__STAGEBH CYREG_DFB0_STAGEBH
#define Filter_DFB__STAGEBM CYREG_DFB0_STAGEBM

/* USBUART_dm */
#define USBUART_dm__0__MASK 0x80u
#define USBUART_dm__0__PC CYREG_IO_PC_PRT15_7_6_PC1
#define USBUART_dm__0__PORT 15
#define USBUART_dm__0__SHIFT 7
#define USBUART_dm__AG CYREG_PRT15_AG
#define USBUART_dm__AMUX CYREG_PRT15_AMUX
#define USBUART_dm__BIE CYREG_PRT15_BIE
#define USBUART_dm__BIT_MASK CYREG_PRT15_BIT_MASK
#define USBUART_dm__BYP CYREG_PRT15_BYP
#define USBUART_dm__CTL CYREG_PRT15_CTL
#define USBUART_dm__DM0 CYREG_PRT15_DM0
#define USBUART_dm__DM1 CYREG_PRT15_DM1
#define USBUART_dm__DM2 CYREG_PRT15_DM2
#define USBUART_dm__DR CYREG_PRT15_DR
#define USBUART_dm__INP_DIS CYREG_PRT15_INP_DIS
#define USBUART_dm__LCD_COM_SEG CYREG_PRT15_LCD_COM_SEG
#define USBUART_dm__LCD_EN CYREG_PRT15_LCD_EN
#define USBUART_dm__PORT 15
#define USBUART_dm__PRT CYREG_PRT15_PRT
#define USBUART_dm__PRTDSI__CAPS_SEL CYREG_PRT15_CAPS_SEL
#define USBUART_dm__PRTDSI__DBL_SYNC_IN CYREG_PRT15_DBL_SYNC_IN
#define USBUART_dm__PRTDSI__OE_SEL0 CYREG_PRT15_OE_SEL0
#define USBUART_dm__PRTDSI__OE_SEL1 CYREG_PRT15_OE_SEL1
#define USBUART_dm__PRTDSI__OUT_SEL0 CYREG_PRT15_OUT_SEL0
#define USBUART_dm__PRTDSI__OUT_SEL1 CYREG_PRT15_OUT_SEL1
#define USBUART_dm__PRTDSI__SYNC_OUT CYREG_PRT15_SYNC_OUT
#define USBUART_dm__PS CYREG_PRT15_PS
#define USBUART_dm__SLW CYREG_PRT15_SLW
#define USBUART_dm__dm__MASK 0x80u
#define USBUART_dm__dm__PC CYREG_IO_PC_PRT15_7_6_PC1
#define USBUART_dm__dm__PORT 15
#define USBUART_dm__dm__SHIFT 7

/* USBUART_dp */
#define USBUART_dp__0__MASK 0x40u
#define USBUART_dp__0__PC CYREG_IO_PC_PRT15_7_6_PC0
#define USBUART_dp__0__PORT 15
#define USBUART_dp__0__SHIFT 6
#define USBUART_dp__AG CYREG_PRT15_AG
#define USBUART_dp__AMUX CYREG_PRT15_AMUX
#define USBUART_dp__BIE CYREG_PRT15_BIE
#define USBUART_dp__BIT_MASK CYREG_PRT15_BIT_MASK
#define USBUART_dp__BYP CYREG_PRT15_BYP
#define USBUART_dp__CTL CYREG_PRT15_CTL
#define USBUART_dp__DM0 CYREG_PRT15_DM0
#define USBUART_dp__DM1 CYREG_PRT15_DM1
#define USBUART_dp__DM2 CYREG_PRT15_DM2
#define USBUART_dp__DR CYREG_PRT15_DR
#define USBUART_dp__INP_DIS CYREG_PRT15_INP_DIS
#define USBUART_dp__LCD_COM_SEG CYREG_PRT15_LCD_COM_SEG
#define USBUART_dp__LCD_EN CYREG_PRT15_LCD_EN
#define USBUART_dp__PORT 15
#define USBUART_dp__PRT CYREG_PRT15_PRT
#define USBUART_dp__PRTDSI__CAPS_SEL CYREG_PRT15_CAPS_SEL
#define USBUART_dp__PRTDSI__DBL_SYNC_IN CYREG_PRT15_DBL_SYNC_IN
#define USBUART_dp__PRTDSI__OE_SEL0 CYREG_PRT15_OE_SEL0
#define USBUART_dp__PRTDSI__OE_SEL1 CYREG_PRT15_OE_SEL1
#define USBUART_dp__PRTDSI__OUT_SEL0 CYREG_PRT15_OUT_SEL0
#define USBUART_dp__PRTDSI__OUT_SEL1 CYREG_PRT15_OUT_SEL1
#define USBUART_dp__PRTDSI__SYNC_OUT CYREG_PRT15_SYNC_OUT
#define USBUART_dp__PS CYREG_PRT15_PS
#define USBUART_dp__SLW CYREG_PRT15_SLW
#define USBUART_dp__dp__MASK 0x40u
#define USBUART_dp__dp__PC CYREG_IO_PC_PRT15_7_6_PC0
#define USBUART_dp__dp__PORT 15
#define USBUART_dp__dp__SHIFT 6

/* ADC_DSM4 */
#define ADC_DSM4__BUF0 CYREG_DSM0_BUF0
#define ADC_DSM4__BUF1 CYREG_DSM0_BUF1
#define ADC_DSM4__BUF2 CYREG_DSM0_BUF2
#define ADC_DSM4__BUF3 CYREG_DSM0_BUF3
#define ADC_DSM4__CLK CYREG_DSM0_CLK
#define ADC_DSM4__CR0 CYREG_DSM0_CR0
#define ADC_DSM4__CR1 CYREG_DSM0_CR1
#define ADC_DSM4__CR10 CYREG_DSM0_CR10
#define ADC_DSM4__CR11 CYREG_DSM0_CR11
#define ADC_DSM4__CR12 CYREG_DSM0_CR12
#define ADC_DSM4__CR13 CYREG_DSM0_CR13
#define ADC_DSM4__CR14 CYREG_DSM0_CR14
#define ADC_DSM4__CR15 CYREG_DSM0_CR15
#define ADC_DSM4__CR16 CYREG_DSM0_CR16
#define ADC_DSM4__CR17 CYREG_DSM0_CR17
#define ADC_DSM4__CR2 CYREG_DSM0_CR2
#define ADC_DSM4__CR3 CYREG_DSM0_CR3
#define ADC_DSM4__CR4 CYREG_DSM0_CR4
#define ADC_DSM4__CR5 CYREG_DSM0_CR5
#define ADC_DSM4__CR6 CYREG_DSM0_CR6
#define ADC_DSM4__CR7 CYREG_DSM0_CR7
#define ADC_DSM4__CR8 CYREG_DSM0_CR8
#define ADC_DSM4__CR9 CYREG_DSM0_CR9
#define ADC_DSM4__DEM0 CYREG_DSM0_DEM0
#define ADC_DSM4__DEM1 CYREG_DSM0_DEM1
#define ADC_DSM4__MISC CYREG_DSM0_MISC
#define ADC_DSM4__OUT0 CYREG_DSM0_OUT0
#define ADC_DSM4__OUT1 CYREG_DSM0_OUT1
#define ADC_DSM4__REF0 CYREG_DSM0_REF0
#define ADC_DSM4__REF1 CYREG_DSM0_REF1
#define ADC_DSM4__REF2 CYREG_DSM0_REF2
#define ADC_DSM4__REF3 CYREG_DSM0_REF3
#define ADC_DSM4__RSVD1 CYREG_DSM0_RSVD1
#define ADC_DSM4__SW0 CYREG_DSM0_SW0
#define ADC_DSM4__SW2 CYREG_DSM0_SW2
#define ADC_DSM4__SW3 CYREG_DSM0_SW3
#define ADC_DSM4__SW4 CYREG_DSM0_SW4
#define ADC_DSM4__SW6 CYREG_DSM0_SW6
#define ADC_DSM4__TR0 CYREG_NPUMP_DSM_TR0
#define ADC_DSM4__TST0 CYREG_DSM0_TST0
#define ADC_DSM4__TST1 CYREG_DSM0_TST1

/* TP14_OUT */
#define TP14_OUT__0__MASK 0x10u
#define TP14_OUT__0__PC CYREG_PRT1_PC4
#define TP14_OUT__0__PORT 1
#define TP14_OUT__0__SHIFT 4
#define TP14_OUT__AG CYREG_PRT1_AG
#define TP14_OUT__AMUX CYREG_PRT1_AMUX
#define TP14_OUT__BIE CYREG_PRT1_BIE
#define TP14_OUT__BIT_MASK CYREG_PRT1_BIT_MASK
#define TP14_OUT__BYP CYREG_PRT1_BYP
#define TP14_OUT__CTL CYREG_PRT1_CTL
#define TP14_OUT__DM0 CYREG_PRT1_DM0
#define TP14_OUT__DM1 CYREG_PRT1_DM1
#define TP14_OUT__DM2 CYREG_PRT1_DM2
#define TP14_OUT__DR CYREG_PRT1_DR
#define TP14_OUT__INP_DIS CYREG_PRT1_INP_DIS
#define TP14_OUT__LCD_COM_SEG CYREG_PRT1_LCD_COM_SEG
#define TP14_OUT__LCD_EN CYREG_PRT1_LCD_EN
#define TP14_OUT__MASK 0x10u
#define TP14_OUT__PORT 1
#define TP14_OUT__PRT CYREG_PRT1_PRT
#define TP14_OUT__PRTDSI__CAPS_SEL CYREG_PRT1_CAPS_SEL
#define TP14_OUT__PRTDSI__DBL_SYNC_IN CYREG_PRT1_DBL_SYNC_IN
#define TP14_OUT__PRTDSI__OE_SEL0 CYREG_PRT1_OE_SEL0
#define TP14_OUT__PRTDSI__OE_SEL1 CYREG_PRT1_OE_SEL1
#define TP14_OUT__PRTDSI__OUT_SEL0 CYREG_PRT1_OUT_SEL0
#define TP14_OUT__PRTDSI__OUT_SEL1 CYREG_PRT1_OUT_SEL1
#define TP14_OUT__PRTDSI__SYNC_OUT CYREG_PRT1_SYNC_OUT
#define TP14_OUT__PS CYREG_PRT1_PS
#define TP14_OUT__SHIFT 4
#define TP14_OUT__SLW CYREG_PRT1_SLW

/* ADC_DEC */
#define ADC_DEC__COHER CYREG_DEC_COHER
#define ADC_DEC__CR CYREG_DEC_CR
#define ADC_DEC__DR1 CYREG_DEC_DR1
#define ADC_DEC__DR2 CYREG_DEC_DR2
#define ADC_DEC__DR2H CYREG_DEC_DR2H
#define ADC_DEC__GCOR CYREG_DEC_GCOR
#define ADC_DEC__GCORH CYREG_DEC_GCORH
#define ADC_DEC__GVAL CYREG_DEC_GVAL
#define ADC_DEC__OCOR CYREG_DEC_OCOR
#define ADC_DEC__OCORH CYREG_DEC_OCORH
#define ADC_DEC__OCORM CYREG_DEC_OCORM
#define ADC_DEC__OUTSAMP CYREG_DEC_OUTSAMP
#define ADC_DEC__OUTSAMPH CYREG_DEC_OUTSAMPH
#define ADC_DEC__OUTSAMPM CYREG_DEC_OUTSAMPM
#define ADC_DEC__OUTSAMPS CYREG_DEC_OUTSAMPS
#define ADC_DEC__PM_ACT_CFG CYREG_PM_ACT_CFG10
#define ADC_DEC__PM_ACT_MSK 0x01u
#define ADC_DEC__PM_STBY_CFG CYREG_PM_STBY_CFG10
#define ADC_DEC__PM_STBY_MSK 0x01u
#define ADC_DEC__SHIFT1 CYREG_DEC_SHIFT1
#define ADC_DEC__SHIFT2 CYREG_DEC_SHIFT2
#define ADC_DEC__SR CYREG_DEC_SR
#define ADC_DEC__TRIM__M1 CYREG_FLSHID_CUST_TABLES_DEC_M1
#define ADC_DEC__TRIM__M2 CYREG_FLSHID_CUST_TABLES_DEC_M2
#define ADC_DEC__TRIM__M3 CYREG_FLSHID_CUST_TABLES_DEC_M3
#define ADC_DEC__TRIM__M4 CYREG_FLSHID_CUST_TABLES_DEC_M4
#define ADC_DEC__TRIM__M5 CYREG_FLSHID_CUST_TABLES_DEC_M5
#define ADC_DEC__TRIM__M6 CYREG_FLSHID_CUST_TABLES_DEC_M6
#define ADC_DEC__TRIM__M7 CYREG_FLSHID_CUST_TABLES_DEC_M7
#define ADC_DEC__TRIM__M8 CYREG_FLSHID_CUST_TABLES_DEC_M8

/* ADC_IRQ */
#define ADC_IRQ__ES2_PATCH 0
#define ADC_IRQ__INTC_CLR_EN_REG CYREG_INTC_CLR_EN3
#define ADC_IRQ__INTC_CLR_PD_REG CYREG_INTC_CLR_PD3
#define ADC_IRQ__INTC_MASK 0x20u
#define ADC_IRQ__INTC_NUMBER 29
#define ADC_IRQ__INTC_PRIOR_NUM 7
#define ADC_IRQ__INTC_PRIOR_REG CYREG_INTC_PRIOR29
#define ADC_IRQ__INTC_SET_EN_REG CYREG_INTC_SET_EN3
#define ADC_IRQ__INTC_SET_PD_REG CYREG_INTC_SET_PD3
#define ADC_IRQ__INTC_VECT (CYREG_INTC_VECT_MBASE+0x3Au)

/* TP2_OUT */
#define TP2_OUT__0__MASK 0x10u
#define TP2_OUT__0__PC CYREG_PRT0_PC4
#define TP2_OUT__0__PORT 0
#define TP2_OUT__0__SHIFT 4
#define TP2_OUT__AG CYREG_PRT0_AG
#define TP2_OUT__AMUX CYREG_PRT0_AMUX
#define TP2_OUT__BIE CYREG_PRT0_BIE
#define TP2_OUT__BIT_MASK CYREG_PRT0_BIT_MASK
#define TP2_OUT__BYP CYREG_PRT0_BYP
#define TP2_OUT__CTL CYREG_PRT0_CTL
#define TP2_OUT__DM0 CYREG_PRT0_DM0
#define TP2_OUT__DM1 CYREG_PRT0_DM1
#define TP2_OUT__DM2 CYREG_PRT0_DM2
#define TP2_OUT__DR CYREG_PRT0_DR
#define TP2_OUT__INP_DIS CYREG_PRT0_INP_DIS
#define TP2_OUT__LCD_COM_SEG CYREG_PRT0_LCD_COM_SEG
#define TP2_OUT__LCD_EN CYREG_PRT0_LCD_EN
#define TP2_OUT__MASK 0x10u
#define TP2_OUT__PORT 0
#define TP2_OUT__PRT CYREG_PRT0_PRT
#define TP2_OUT__PRTDSI__CAPS_SEL CYREG_PRT0_CAPS_SEL
#define TP2_OUT__PRTDSI__DBL_SYNC_IN CYREG_PRT0_DBL_SYNC_IN
#define TP2_OUT__PRTDSI__OE_SEL0 CYREG_PRT0_OE_SEL0
#define TP2_OUT__PRTDSI__OE_SEL1 CYREG_PRT0_OE_SEL1
#define TP2_OUT__PRTDSI__OUT_SEL0 CYREG_PRT0_OUT_SEL0
#define TP2_OUT__PRTDSI__OUT_SEL1 CYREG_PRT0_OUT_SEL1
#define TP2_OUT__PRTDSI__SYNC_OUT CYREG_PRT0_SYNC_OUT
#define TP2_OUT__PS CYREG_PRT0_PS
#define TP2_OUT__SHIFT 4
#define TP2_OUT__SLW CYREG_PRT0_SLW

/* ADCREF */
#define ADCREF__0__MASK 0x08u
#define ADCREF__0__PC CYREG_PRT2_PC3
#define ADCREF__0__PORT 2
#define ADCREF__0__SHIFT 3
#define ADCREF__AG CYREG_PRT2_AG
#define ADCREF__AMUX CYREG_PRT2_AMUX
#define ADCREF__BIE CYREG_PRT2_BIE
#define ADCREF__BIT_MASK CYREG_PRT2_BIT_MASK
#define ADCREF__BYP CYREG_PRT2_BYP
#define ADCREF__CTL CYREG_PRT2_CTL
#define ADCREF__DM0 CYREG_PRT2_DM0
#define ADCREF__DM1 CYREG_PRT2_DM1
#define ADCREF__DM2 CYREG_PRT2_DM2
#define ADCREF__DR CYREG_PRT2_DR
#define ADCREF__INP_DIS CYREG_PRT2_INP_DIS
#define ADCREF__LCD_COM_SEG CYREG_PRT2_LCD_COM_SEG
#define ADCREF__LCD_EN CYREG_PRT2_LCD_EN
#define ADCREF__PORT 2
#define ADCREF__PRT CYREG_PRT2_PRT
#define ADCREF__PRTDSI__CAPS_SEL CYREG_PRT2_CAPS_SEL
#define ADCREF__PRTDSI__DBL_SYNC_IN CYREG_PRT2_DBL_SYNC_IN
#define ADCREF__PRTDSI__OE_SEL0 CYREG_PRT2_OE_SEL0
#define ADCREF__PRTDSI__OE_SEL1 CYREG_PRT2_OE_SEL1
#define ADCREF__PRTDSI__OUT_SEL0 CYREG_PRT2_OUT_SEL0
#define ADCREF__PRTDSI__OUT_SEL1 CYREG_PRT2_OUT_SEL1
#define ADCREF__PRTDSI__SYNC_OUT CYREG_PRT2_SYNC_OUT
#define ADCREF__PS CYREG_PRT2_PS
#define ADCREF__SLW CYREG_PRT2_SLW

/* REDLED */
#define REDLED__0__MASK 0x01u
#define REDLED__0__PC CYREG_PRT0_PC0
#define REDLED__0__PORT 0
#define REDLED__0__SHIFT 0
#define REDLED__AG CYREG_PRT0_AG
#define REDLED__AMUX CYREG_PRT0_AMUX
#define REDLED__BIE CYREG_PRT0_BIE
#define REDLED__BIT_MASK CYREG_PRT0_BIT_MASK
#define REDLED__BYP CYREG_PRT0_BYP
#define REDLED__CTL CYREG_PRT0_CTL
#define REDLED__DM0 CYREG_PRT0_DM0
#define REDLED__DM1 CYREG_PRT0_DM1
#define REDLED__DM2 CYREG_PRT0_DM2
#define REDLED__DR CYREG_PRT0_DR
#define REDLED__INP_DIS CYREG_PRT0_INP_DIS
#define REDLED__LCD_COM_SEG CYREG_PRT0_LCD_COM_SEG
#define REDLED__LCD_EN CYREG_PRT0_LCD_EN
#define REDLED__MASK 0x01u
#define REDLED__PORT 0
#define REDLED__PRT CYREG_PRT0_PRT
#define REDLED__PRTDSI__CAPS_SEL CYREG_PRT0_CAPS_SEL
#define REDLED__PRTDSI__DBL_SYNC_IN CYREG_PRT0_DBL_SYNC_IN
#define REDLED__PRTDSI__OE_SEL0 CYREG_PRT0_OE_SEL0
#define REDLED__PRTDSI__OE_SEL1 CYREG_PRT0_OE_SEL1
#define REDLED__PRTDSI__OUT_SEL0 CYREG_PRT0_OUT_SEL0
#define REDLED__PRTDSI__OUT_SEL1 CYREG_PRT0_OUT_SEL1
#define REDLED__PRTDSI__SYNC_OUT CYREG_PRT0_SYNC_OUT
#define REDLED__PS CYREG_PRT0_PS
#define REDLED__SHIFT 0
#define REDLED__SLW CYREG_PRT0_SLW

/* FracN */
#define FracN_FracHi__0__MASK 0x01u
#define FracN_FracHi__0__POS 0
#define FracN_FracHi__16BIT_CONTROL_AUX_CTL_REG CYREG_B0_UDB04_05_ACTL
#define FracN_FracHi__16BIT_CONTROL_CONTROL_REG CYREG_B0_UDB04_05_CTL
#define FracN_FracHi__16BIT_CONTROL_COUNT_REG CYREG_B0_UDB04_05_CTL
#define FracN_FracHi__16BIT_COUNT_CONTROL_REG CYREG_B0_UDB04_05_CTL
#define FracN_FracHi__16BIT_COUNT_COUNT_REG CYREG_B0_UDB04_05_CTL
#define FracN_FracHi__16BIT_MASK_MASK_REG CYREG_B0_UDB04_05_MSK
#define FracN_FracHi__16BIT_MASK_PERIOD_REG CYREG_B0_UDB04_05_MSK
#define FracN_FracHi__16BIT_PERIOD_MASK_REG CYREG_B0_UDB04_05_MSK
#define FracN_FracHi__16BIT_PERIOD_PERIOD_REG CYREG_B0_UDB04_05_MSK
#define FracN_FracHi__1__MASK 0x02u
#define FracN_FracHi__1__POS 1
#define FracN_FracHi__2__MASK 0x04u
#define FracN_FracHi__2__POS 2
#define FracN_FracHi__3__MASK 0x08u
#define FracN_FracHi__3__POS 3
#define FracN_FracHi__4__MASK 0x10u
#define FracN_FracHi__4__POS 4
#define FracN_FracHi__5__MASK 0x20u
#define FracN_FracHi__5__POS 5
#define FracN_FracHi__7__MASK 0x80u
#define FracN_FracHi__7__POS 7
#define FracN_FracHi__CONTROL_AUX_CTL_REG CYREG_B0_UDB04_ACTL
#define FracN_FracHi__CONTROL_REG CYREG_B0_UDB04_CTL
#define FracN_FracHi__CONTROL_ST_REG CYREG_B0_UDB04_ST_CTL
#define FracN_FracHi__COUNT_REG CYREG_B0_UDB04_CTL
#define FracN_FracHi__COUNT_ST_REG CYREG_B0_UDB04_ST_CTL
#define FracN_FracHi__MASK 0xBFu
#define FracN_FracHi__MASK_CTL_AUX_CTL_REG CYREG_B0_UDB04_MSK_ACTL
#define FracN_FracHi__PERIOD_REG CYREG_B0_UDB04_MSK
#define FracN_FracHi__PER_CTL_AUX_CTL_REG CYREG_B0_UDB04_MSK_ACTL
#define FracN_FracLo__0__MASK 0x01u
#define FracN_FracLo__0__POS 0
#define FracN_FracLo__16BIT_CONTROL_AUX_CTL_REG CYREG_B0_UDB03_04_ACTL
#define FracN_FracLo__16BIT_CONTROL_CONTROL_REG CYREG_B0_UDB03_04_CTL
#define FracN_FracLo__16BIT_CONTROL_COUNT_REG CYREG_B0_UDB03_04_CTL
#define FracN_FracLo__16BIT_COUNT_CONTROL_REG CYREG_B0_UDB03_04_CTL
#define FracN_FracLo__16BIT_COUNT_COUNT_REG CYREG_B0_UDB03_04_CTL
#define FracN_FracLo__16BIT_MASK_MASK_REG CYREG_B0_UDB03_04_MSK
#define FracN_FracLo__16BIT_MASK_PERIOD_REG CYREG_B0_UDB03_04_MSK
#define FracN_FracLo__16BIT_PERIOD_MASK_REG CYREG_B0_UDB03_04_MSK
#define FracN_FracLo__16BIT_PERIOD_PERIOD_REG CYREG_B0_UDB03_04_MSK
#define FracN_FracLo__1__MASK 0x02u
#define FracN_FracLo__1__POS 1
#define FracN_FracLo__2__MASK 0x04u
#define FracN_FracLo__2__POS 2
#define FracN_FracLo__3__MASK 0x08u
#define FracN_FracLo__3__POS 3
#define FracN_FracLo__4__MASK 0x10u
#define FracN_FracLo__4__POS 4
#define FracN_FracLo__5__MASK 0x20u
#define FracN_FracLo__5__POS 5
#define FracN_FracLo__6__MASK 0x40u
#define FracN_FracLo__6__POS 6
#define FracN_FracLo__7__MASK 0x80u
#define FracN_FracLo__7__POS 7
#define FracN_FracLo__CONTROL_AUX_CTL_REG CYREG_B0_UDB03_ACTL
#define FracN_FracLo__CONTROL_REG CYREG_B0_UDB03_CTL
#define FracN_FracLo__CONTROL_ST_REG CYREG_B0_UDB03_ST_CTL
#define FracN_FracLo__COUNT_REG CYREG_B0_UDB03_CTL
#define FracN_FracLo__COUNT_ST_REG CYREG_B0_UDB03_ST_CTL
#define FracN_FracLo__MASK 0xFFu
#define FracN_FracLo__MASK_CTL_AUX_CTL_REG CYREG_B0_UDB03_MSK_ACTL
#define FracN_FracLo__PERIOD_REG CYREG_B0_UDB03_MSK
#define FracN_FracLo__PER_CTL_AUX_CTL_REG CYREG_B0_UDB03_MSK_ACTL
#define FracN_PLL_N__0__MASK 0x01u
#define FracN_PLL_N__0__POS 0
#define FracN_PLL_N__16BIT_CONTROL_AUX_CTL_REG CYREG_B0_UDB06_07_ACTL
#define FracN_PLL_N__16BIT_CONTROL_CONTROL_REG CYREG_B0_UDB06_07_CTL
#define FracN_PLL_N__16BIT_CONTROL_COUNT_REG CYREG_B0_UDB06_07_CTL
#define FracN_PLL_N__16BIT_COUNT_CONTROL_REG CYREG_B0_UDB06_07_CTL
#define FracN_PLL_N__16BIT_COUNT_COUNT_REG CYREG_B0_UDB06_07_CTL
#define FracN_PLL_N__16BIT_MASK_MASK_REG CYREG_B0_UDB06_07_MSK
#define FracN_PLL_N__16BIT_MASK_PERIOD_REG CYREG_B0_UDB06_07_MSK
#define FracN_PLL_N__16BIT_PERIOD_MASK_REG CYREG_B0_UDB06_07_MSK
#define FracN_PLL_N__16BIT_PERIOD_PERIOD_REG CYREG_B0_UDB06_07_MSK
#define FracN_PLL_N__1__MASK 0x02u
#define FracN_PLL_N__1__POS 1
#define FracN_PLL_N__2__MASK 0x04u
#define FracN_PLL_N__2__POS 2
#define FracN_PLL_N__3__MASK 0x08u
#define FracN_PLL_N__3__POS 3
#define FracN_PLL_N__4__MASK 0x10u
#define FracN_PLL_N__4__POS 4
#define FracN_PLL_N__5__MASK 0x20u
#define FracN_PLL_N__5__POS 5
#define FracN_PLL_N__6__MASK 0x40u
#define FracN_PLL_N__6__POS 6
#define FracN_PLL_N__CONTROL_AUX_CTL_REG CYREG_B0_UDB06_ACTL
#define FracN_PLL_N__CONTROL_REG CYREG_B0_UDB06_CTL
#define FracN_PLL_N__CONTROL_ST_REG CYREG_B0_UDB06_ST_CTL
#define FracN_PLL_N__COUNT_REG CYREG_B0_UDB06_CTL
#define FracN_PLL_N__COUNT_ST_REG CYREG_B0_UDB06_ST_CTL
#define FracN_PLL_N__MASK 0x7Fu
#define FracN_PLL_N__MASK_CTL_AUX_CTL_REG CYREG_B0_UDB06_MSK_ACTL
#define FracN_PLL_N__PERIOD_REG CYREG_B0_UDB06_MSK
#define FracN_PLL_N__PER_CTL_AUX_CTL_REG CYREG_B0_UDB06_MSK_ACTL
#define FracN_PLL_P_Reg__0__MASK 0x01u
#define FracN_PLL_P_Reg__0__POS 0
#define FracN_PLL_P_Reg__16BIT_STATUS_AUX_CTL_REG CYREG_B0_UDB01_02_ACTL
#define FracN_PLL_P_Reg__16BIT_STATUS_REG CYREG_B0_UDB01_02_ST
#define FracN_PLL_P_Reg__1__MASK 0x02u
#define FracN_PLL_P_Reg__1__POS 1
#define FracN_PLL_P_Reg__2__MASK 0x04u
#define FracN_PLL_P_Reg__2__POS 2
#define FracN_PLL_P_Reg__3__MASK 0x08u
#define FracN_PLL_P_Reg__3__POS 3
#define FracN_PLL_P_Reg__4__MASK 0x10u
#define FracN_PLL_P_Reg__4__POS 4
#define FracN_PLL_P_Reg__5__MASK 0x20u
#define FracN_PLL_P_Reg__5__POS 5
#define FracN_PLL_P_Reg__6__MASK 0x40u
#define FracN_PLL_P_Reg__6__POS 6
#define FracN_PLL_P_Reg__MASK 0x7Fu
#define FracN_PLL_P_Reg__MASK_REG CYREG_B0_UDB01_MSK
#define FracN_PLL_P_Reg__STATUS_AUX_CTL_REG CYREG_B0_UDB01_ACTL
#define FracN_PLL_P_Reg__STATUS_REG CYREG_B0_UDB01_ST

/* ICHAN */
#define ICHAN__0__MASK 0x20u
#define ICHAN__0__PC CYREG_PRT2_PC5
#define ICHAN__0__PORT 2
#define ICHAN__0__SHIFT 5
#define ICHAN__AG CYREG_PRT2_AG
#define ICHAN__AMUX CYREG_PRT2_AMUX
#define ICHAN__BIE CYREG_PRT2_BIE
#define ICHAN__BIT_MASK CYREG_PRT2_BIT_MASK
#define ICHAN__BYP CYREG_PRT2_BYP
#define ICHAN__CTL CYREG_PRT2_CTL
#define ICHAN__DM0 CYREG_PRT2_DM0
#define ICHAN__DM1 CYREG_PRT2_DM1
#define ICHAN__DM2 CYREG_PRT2_DM2
#define ICHAN__DR CYREG_PRT2_DR
#define ICHAN__INP_DIS CYREG_PRT2_INP_DIS
#define ICHAN__LCD_COM_SEG CYREG_PRT2_LCD_COM_SEG
#define ICHAN__LCD_EN CYREG_PRT2_LCD_EN
#define ICHAN__PORT 2
#define ICHAN__PRT CYREG_PRT2_PRT
#define ICHAN__PRTDSI__CAPS_SEL CYREG_PRT2_CAPS_SEL
#define ICHAN__PRTDSI__DBL_SYNC_IN CYREG_PRT2_DBL_SYNC_IN
#define ICHAN__PRTDSI__OE_SEL0 CYREG_PRT2_OE_SEL0
#define ICHAN__PRTDSI__OE_SEL1 CYREG_PRT2_OE_SEL1
#define ICHAN__PRTDSI__OUT_SEL0 CYREG_PRT2_OUT_SEL0
#define ICHAN__PRTDSI__OUT_SEL1 CYREG_PRT2_OUT_SEL1
#define ICHAN__PRTDSI__SYNC_OUT CYREG_PRT2_SYNC_OUT
#define ICHAN__PS CYREG_PRT2_PS
#define ICHAN__SLW CYREG_PRT2_SLW

/* IQMUX */
#define IQMUX_ctrl_reg__0__MASK 0x01u
#define IQMUX_ctrl_reg__0__POS 0
#define IQMUX_ctrl_reg__16BIT_CONTROL_AUX_CTL_REG CYREG_B0_UDB13_14_ACTL
#define IQMUX_ctrl_reg__16BIT_CONTROL_CONTROL_REG CYREG_B0_UDB13_14_CTL
#define IQMUX_ctrl_reg__16BIT_CONTROL_COUNT_REG CYREG_B0_UDB13_14_CTL
#define IQMUX_ctrl_reg__16BIT_COUNT_CONTROL_REG CYREG_B0_UDB13_14_CTL
#define IQMUX_ctrl_reg__16BIT_COUNT_COUNT_REG CYREG_B0_UDB13_14_CTL
#define IQMUX_ctrl_reg__16BIT_MASK_MASK_REG CYREG_B0_UDB13_14_MSK
#define IQMUX_ctrl_reg__16BIT_MASK_PERIOD_REG CYREG_B0_UDB13_14_MSK
#define IQMUX_ctrl_reg__16BIT_PERIOD_MASK_REG CYREG_B0_UDB13_14_MSK
#define IQMUX_ctrl_reg__16BIT_PERIOD_PERIOD_REG CYREG_B0_UDB13_14_MSK
#define IQMUX_ctrl_reg__1__MASK 0x02u
#define IQMUX_ctrl_reg__1__POS 1
#define IQMUX_ctrl_reg__CONTROL_AUX_CTL_REG CYREG_B0_UDB13_ACTL
#define IQMUX_ctrl_reg__CONTROL_REG CYREG_B0_UDB13_CTL
#define IQMUX_ctrl_reg__CONTROL_ST_REG CYREG_B0_UDB13_ST_CTL
#define IQMUX_ctrl_reg__COUNT_REG CYREG_B0_UDB13_CTL
#define IQMUX_ctrl_reg__COUNT_ST_REG CYREG_B0_UDB13_ST_CTL
#define IQMUX_ctrl_reg__MASK 0x03u
#define IQMUX_ctrl_reg__MASK_CTL_AUX_CTL_REG CYREG_B0_UDB13_MSK_ACTL
#define IQMUX_ctrl_reg__PERIOD_REG CYREG_B0_UDB13_MSK
#define IQMUX_ctrl_reg__PER_CTL_AUX_CTL_REG CYREG_B0_UDB13_MSK_ACTL

/* QCHAN */
#define QCHAN__0__MASK 0x10u
#define QCHAN__0__PC CYREG_PRT2_PC4
#define QCHAN__0__PORT 2
#define QCHAN__0__SHIFT 4
#define QCHAN__AG CYREG_PRT2_AG
#define QCHAN__AMUX CYREG_PRT2_AMUX
#define QCHAN__BIE CYREG_PRT2_BIE
#define QCHAN__BIT_MASK CYREG_PRT2_BIT_MASK
#define QCHAN__BYP CYREG_PRT2_BYP
#define QCHAN__CTL CYREG_PRT2_CTL
#define QCHAN__DM0 CYREG_PRT2_DM0
#define QCHAN__DM1 CYREG_PRT2_DM1
#define QCHAN__DM2 CYREG_PRT2_DM2
#define QCHAN__DR CYREG_PRT2_DR
#define QCHAN__INP_DIS CYREG_PRT2_INP_DIS
#define QCHAN__LCD_COM_SEG CYREG_PRT2_LCD_COM_SEG
#define QCHAN__LCD_EN CYREG_PRT2_LCD_EN
#define QCHAN__PORT 2
#define QCHAN__PRT CYREG_PRT2_PRT
#define QCHAN__PRTDSI__CAPS_SEL CYREG_PRT2_CAPS_SEL
#define QCHAN__PRTDSI__DBL_SYNC_IN CYREG_PRT2_DBL_SYNC_IN
#define QCHAN__PRTDSI__OE_SEL0 CYREG_PRT2_OE_SEL0
#define QCHAN__PRTDSI__OE_SEL1 CYREG_PRT2_OE_SEL1
#define QCHAN__PRTDSI__OUT_SEL0 CYREG_PRT2_OUT_SEL0
#define QCHAN__PRTDSI__OUT_SEL1 CYREG_PRT2_OUT_SEL1
#define QCHAN__PRTDSI__SYNC_OUT CYREG_PRT2_SYNC_OUT
#define QCHAN__PS CYREG_PRT2_PS
#define QCHAN__SLW CYREG_PRT2_SLW

/* ICLK */
#define ICLK__0__MASK 0x08u
#define ICLK__0__PC CYREG_PRT12_PC3
#define ICLK__0__PORT 12
#define ICLK__0__SHIFT 3
#define ICLK__AG CYREG_PRT12_AG
#define ICLK__BIE CYREG_PRT12_BIE
#define ICLK__BIT_MASK CYREG_PRT12_BIT_MASK
#define ICLK__BYP CYREG_PRT12_BYP
#define ICLK__DM0 CYREG_PRT12_DM0
#define ICLK__DM1 CYREG_PRT12_DM1
#define ICLK__DM2 CYREG_PRT12_DM2
#define ICLK__DR CYREG_PRT12_DR
#define ICLK__INP_DIS CYREG_PRT12_INP_DIS
#define ICLK__MASK 0x08u
#define ICLK__PORT 12
#define ICLK__PRT CYREG_PRT12_PRT
#define ICLK__PRTDSI__DBL_SYNC_IN CYREG_PRT12_DBL_SYNC_IN
#define ICLK__PRTDSI__OE_SEL0 CYREG_PRT12_OE_SEL0
#define ICLK__PRTDSI__OE_SEL1 CYREG_PRT12_OE_SEL1
#define ICLK__PRTDSI__OUT_SEL0 CYREG_PRT12_OUT_SEL0
#define ICLK__PRTDSI__OUT_SEL1 CYREG_PRT12_OUT_SEL1
#define ICLK__PRTDSI__SYNC_OUT CYREG_PRT12_SYNC_OUT
#define ICLK__PS CYREG_PRT12_PS
#define ICLK__SHIFT 3
#define ICLK__SIO_CFG CYREG_PRT12_SIO_CFG
#define ICLK__SIO_DIFF CYREG_PRT12_SIO_DIFF
#define ICLK__SIO_HYST_EN CYREG_PRT12_SIO_HYST_EN
#define ICLK__SIO_REG_HIFREQ CYREG_PRT12_SIO_REG_HIFREQ
#define ICLK__SLW CYREG_PRT12_SLW

/* IOUT */
#define IOUT__0__MASK 0x40u
#define IOUT__0__PC CYREG_PRT2_PC6
#define IOUT__0__PORT 2
#define IOUT__0__SHIFT 6
#define IOUT__AG CYREG_PRT2_AG
#define IOUT__AMUX CYREG_PRT2_AMUX
#define IOUT__BIE CYREG_PRT2_BIE
#define IOUT__BIT_MASK CYREG_PRT2_BIT_MASK
#define IOUT__BYP CYREG_PRT2_BYP
#define IOUT__CTL CYREG_PRT2_CTL
#define IOUT__DM0 CYREG_PRT2_DM0
#define IOUT__DM1 CYREG_PRT2_DM1
#define IOUT__DM2 CYREG_PRT2_DM2
#define IOUT__DR CYREG_PRT2_DR
#define IOUT__INP_DIS CYREG_PRT2_INP_DIS
#define IOUT__LCD_COM_SEG CYREG_PRT2_LCD_COM_SEG
#define IOUT__LCD_EN CYREG_PRT2_LCD_EN
#define IOUT__PORT 2
#define IOUT__PRT CYREG_PRT2_PRT
#define IOUT__PRTDSI__CAPS_SEL CYREG_PRT2_CAPS_SEL
#define IOUT__PRTDSI__DBL_SYNC_IN CYREG_PRT2_DBL_SYNC_IN
#define IOUT__PRTDSI__OE_SEL0 CYREG_PRT2_OE_SEL0
#define IOUT__PRTDSI__OE_SEL1 CYREG_PRT2_OE_SEL1
#define IOUT__PRTDSI__OUT_SEL0 CYREG_PRT2_OUT_SEL0
#define IOUT__PRTDSI__OUT_SEL1 CYREG_PRT2_OUT_SEL1
#define IOUT__PRTDSI__SYNC_OUT CYREG_PRT2_SYNC_OUT
#define IOUT__PS CYREG_PRT2_PS
#define IOUT__SLW CYREG_PRT2_SLW

/* QCLK */
#define QCLK__0__MASK 0x04u
#define QCLK__0__PC CYREG_PRT12_PC2
#define QCLK__0__PORT 12
#define QCLK__0__SHIFT 2
#define QCLK__AG CYREG_PRT12_AG
#define QCLK__BIE CYREG_PRT12_BIE
#define QCLK__BIT_MASK CYREG_PRT12_BIT_MASK
#define QCLK__BYP CYREG_PRT12_BYP
#define QCLK__DM0 CYREG_PRT12_DM0
#define QCLK__DM1 CYREG_PRT12_DM1
#define QCLK__DM2 CYREG_PRT12_DM2
#define QCLK__DR CYREG_PRT12_DR
#define QCLK__INP_DIS CYREG_PRT12_INP_DIS
#define QCLK__MASK 0x04u
#define QCLK__PORT 12
#define QCLK__PRT CYREG_PRT12_PRT
#define QCLK__PRTDSI__DBL_SYNC_IN CYREG_PRT12_DBL_SYNC_IN
#define QCLK__PRTDSI__OE_SEL0 CYREG_PRT12_OE_SEL0
#define QCLK__PRTDSI__OE_SEL1 CYREG_PRT12_OE_SEL1
#define QCLK__PRTDSI__OUT_SEL0 CYREG_PRT12_OUT_SEL0
#define QCLK__PRTDSI__OUT_SEL1 CYREG_PRT12_OUT_SEL1
#define QCLK__PRTDSI__SYNC_OUT CYREG_PRT12_SYNC_OUT
#define QCLK__PS CYREG_PRT12_PS
#define QCLK__SHIFT 2
#define QCLK__SIO_CFG CYREG_PRT12_SIO_CFG
#define QCLK__SIO_DIFF CYREG_PRT12_SIO_DIFF
#define QCLK__SIO_HYST_EN CYREG_PRT12_SIO_HYST_EN
#define QCLK__SIO_REG_HIFREQ CYREG_PRT12_SIO_REG_HIFREQ
#define QCLK__SLW CYREG_PRT12_SLW

/* QOUT */
#define QOUT__0__MASK 0x80u
#define QOUT__0__PC CYREG_PRT2_PC7
#define QOUT__0__PORT 2
#define QOUT__0__SHIFT 7
#define QOUT__AG CYREG_PRT2_AG
#define QOUT__AMUX CYREG_PRT2_AMUX
#define QOUT__BIE CYREG_PRT2_BIE
#define QOUT__BIT_MASK CYREG_PRT2_BIT_MASK
#define QOUT__BYP CYREG_PRT2_BYP
#define QOUT__CTL CYREG_PRT2_CTL
#define QOUT__DM0 CYREG_PRT2_DM0
#define QOUT__DM1 CYREG_PRT2_DM1
#define QOUT__DM2 CYREG_PRT2_DM2
#define QOUT__DR CYREG_PRT2_DR
#define QOUT__INP_DIS CYREG_PRT2_INP_DIS
#define QOUT__LCD_COM_SEG CYREG_PRT2_LCD_COM_SEG
#define QOUT__LCD_EN CYREG_PRT2_LCD_EN
#define QOUT__PORT 2
#define QOUT__PRT CYREG_PRT2_PRT
#define QOUT__PRTDSI__CAPS_SEL CYREG_PRT2_CAPS_SEL
#define QOUT__PRTDSI__DBL_SYNC_IN CYREG_PRT2_DBL_SYNC_IN
#define QOUT__PRTDSI__OE_SEL0 CYREG_PRT2_OE_SEL0
#define QOUT__PRTDSI__OE_SEL1 CYREG_PRT2_OE_SEL1
#define QOUT__PRTDSI__OUT_SEL0 CYREG_PRT2_OUT_SEL0
#define QOUT__PRTDSI__OUT_SEL1 CYREG_PRT2_OUT_SEL1
#define QOUT__PRTDSI__SYNC_OUT CYREG_PRT2_SYNC_OUT
#define QOUT__PS CYREG_PRT2_PS
#define QOUT__SLW CYREG_PRT2_SLW

/* DMA */
#define DMA_CHANNELS_USED__MASK0 0x00010000u
#define DMA__DRQ_CTL CYREG_IDMUX_DRQ_CTL4
#define DMA__DRQ_NUMBER 16
#define DMA__NUMBEROF_TDS 0
#define DMA__PRIORITY 2
#define DMA__TERMIN_EN 0
#define DMA__TERMIN_SEL 0
#define DMA__TERMOUT0_EN 0
#define DMA__TERMOUT0_SEL 0
#define DMA__TERMOUT1_EN 0
#define DMA__TERMOUT1_SEL 0

/* Miscellaneous */
/* -- WARNING: define names containting LEOPARD or PANTHER are deprecated and will be removed in a future release */
#define CYDEV_BOOTLOADER_IO_COMP_CUSTOM_IO 0
#define CYDEV_DEBUGGING_DPS_SWD 2
#define CYDEV_CONFIG_UNUSED_IO_AllowButWarn 0
#define CYDEV_CONFIGURATION_MODE_COMPRESSED 0
#define CYDEV_CONFIG_FASTBOOT_ENABLED 1
#define CYDEV_CHIP_REV_LEOPARD_PRODUCTION 3
#define CYDEV_CHIP_REVISION_3A_PRODUCTION 3
#define CYDEV_CHIP_MEMBER_3A 1
#define CYDEV_CHIP_FAMILY_PSOC3 1
#define CYDEV_CHIP_DIE_LEOPARD 1
#define CYDEV_CHIP_DIE_EXPECT CYDEV_CHIP_DIE_LEOPARD
#define CYDEV_BOOTLOADER_CHECKSUM_BASIC 0
#define BCLK__BUS_CLK__HZ 56000000U
#define BCLK__BUS_CLK__KHZ 56000U
#define BCLK__BUS_CLK__MHZ 56U
#define CYDEV_APPLICATION_ID 0x0000
#define CYDEV_APPLICATION_VERSION 0x0000
#define CYDEV_BOOTLOADER_CHECKSUM CYDEV_BOOTLOADER_CHECKSUM_BASIC
#define CYDEV_BOOTLOADER_CHECKSUM_CRC 1
#define CYDEV_BOOTLOADER_FAST_VERIFY 0
#define CYDEV_BOOTLOADER_VERSION 0x0000
#define CYDEV_BOOTLOADER_WAIT_COMMAND 1
#define CYDEV_BOOTLOADER_WAIT_TIME 200
#define CYDEV_CHIP_DIE_ACTUAL CYDEV_CHIP_DIE_EXPECT
#define CYDEV_CHIP_DIE_PANTHER 2
#define CYDEV_CHIP_DIE_UNKNOWN 0
#define CYDEV_CHIP_FAMILY_PSOC4 2
#define CYDEV_CHIP_FAMILY_PSOC5 3
#define CYDEV_CHIP_FAMILY_UNKNOWN 0
#define CYDEV_CHIP_FAMILY_USED CYDEV_CHIP_FAMILY_PSOC3
#define CYDEV_CHIP_JTAG_ID 0x1E015069
#define CYDEV_CHIP_MEMBER_5A 2
#define CYDEV_CHIP_MEMBER_UNKNOWN 0
#define CYDEV_CHIP_MEMBER_USED CYDEV_CHIP_MEMBER_3A
#define CYDEV_CHIP_REVISION_3A_ES1 0
#define CYDEV_CHIP_REVISION_3A_ES2 1
#define CYDEV_CHIP_REVISION_3A_ES3 3
#define CYDEV_CHIP_REVISION_5A_ES0 0
#define CYDEV_CHIP_REVISION_5A_ES1 1
#define CYDEV_CHIP_REVISION_5A_PRODUCTION 1
#define CYDEV_CHIP_REVISION_USED CYDEV_CHIP_REVISION_3A_PRODUCTION
#define CYDEV_CHIP_REV_EXPECT CYDEV_CHIP_REV_LEOPARD_PRODUCTION
#define CYDEV_CHIP_REV_LEOPARD_ES1 0
#define CYDEV_CHIP_REV_LEOPARD_ES2 1
#define CYDEV_CHIP_REV_LEOPARD_ES3 3
#define CYDEV_CHIP_REV_PANTHER_ES0 0
#define CYDEV_CHIP_REV_PANTHER_ES1 1
#define CYDEV_CHIP_REV_PANTHER_PRODUCTION 1
#define CYDEV_CONFIGURATION_CLEAR_SRAM 1
#define CYDEV_CONFIGURATION_COMPRESSED 1
#define CYDEV_CONFIGURATION_DMA 0
#define CYDEV_CONFIGURATION_ECC 0
#define CYDEV_CONFIGURATION_IMOENABLED CYDEV_CONFIG_FASTBOOT_ENABLED
#define CYDEV_CONFIGURATION_MODE CYDEV_CONFIGURATION_MODE_COMPRESSED
#define CYDEV_CONFIGURATION_MODE_DMA 2
#define CYDEV_CONFIGURATION_MODE_UNCOMPRESSED 1
#define CYDEV_CONFIG_FORCE_ROUTE 0
#define CYDEV_CONFIG_UNUSED_IO CYDEV_CONFIG_UNUSED_IO_AllowButWarn
#define CYDEV_CONFIG_UNUSED_IO_AllowWithInfo 1
#define CYDEV_CONFIG_UNUSED_IO_Disallowed 2
#define CYDEV_CUSTOM_ID 0x00000000
#define CYDEV_DEBUGGING_DPS CYDEV_DEBUGGING_DPS_SWD
#define CYDEV_DEBUGGING_DPS_Disable 3
#define CYDEV_DEBUGGING_DPS_JTAG_4 1
#define CYDEV_DEBUGGING_DPS_JTAG_5 0
#define CYDEV_DEBUGGING_ENABLE 1
#define CYDEV_DEBUGGING_REQXRES 1
#define CYDEV_DEBUGGING_XRES 1
#define CYDEV_DEBUG_ENABLE_MASK 0x01
#define CYDEV_DEBUG_ENABLE_REGISTER CYREG_MLOGIC_DEBUG
#define CYDEV_DMA_CHANNELS_AVAILABLE 24
#define CYDEV_ECC_ENABLE 0
#define CYDEV_INSTRUCT_CACHE_ENABLED 0
#define CYDEV_PROJ_TYPE 2
#define CYDEV_PROJ_TYPE_BOOTLOADER 1
#define CYDEV_PROJ_TYPE_LOADABLE 2
#define CYDEV_PROJ_TYPE_MULTIAPPBOOTLOADER 3
#define CYDEV_PROJ_TYPE_STANDARD 0
#define CYDEV_PROTECTION_ENABLE 0
#define CYDEV_USB_CLK_OSC_LOCKING_ENABLED_AT_PWR_UP 
#define CYDEV_VDDA 3.3
#define CYDEV_VDDA_MV 3300
#define CYDEV_VDDD 3.3
#define CYDEV_VDDD_MV 3300
#define CYDEV_VDDIO0 3.3
#define CYDEV_VDDIO0_MV 3300
#define CYDEV_VDDIO1 3.3
#define CYDEV_VDDIO1_MV 3300
#define CYDEV_VDDIO2 3.3
#define CYDEV_VDDIO2_MV 3300
#define CYDEV_VDDIO3 3.3
#define CYDEV_VDDIO3_MV 3300
#define CYDEV_VIO0 3.3
#define CYDEV_VIO0_MV 3300
#define CYDEV_VIO1 3.3
#define CYDEV_VIO1_MV 3300
#define CYDEV_VIO2 3.3
#define CYDEV_VIO2_MV 3300
#define CYDEV_VIO3 3.3
#define CYDEV_VIO3_MV 3300
#define CyBtldr_Custom_Interface CYDEV_BOOTLOADER_IO_COMP_CUSTOM_IO
#define CYDEV_BOOTLOADER_ENABLE 0

#endif /* INCLUDED_CYFITTER_H */
